CHAPTER 4: INSTRUCTION SET

These instructions perform a PC relative branch using the content (4 bits) of a memory specified with the [addr6] as a relative address. The branch destination address is [the address next to the branch instruction] + [the contents (0 to 15) of the memory specified with the addr6].

(2)Instructions that access from FFC0H to FFFFH

This area is reserved for the I/O memory in the S1C63 Family and the following instructions are provided to operate the control bits of the peripheral circuits.

An address within FFC0H to FFFFH is specified with the addr6. However the addr6 is handled as 0 to 3FH in the machine codes.

CLR

[addr6],imm2 ...Clears a bit specified with the imm2 in a memory specified with the addr6

SET

[addr6],imm2

...Sets a bit specified with the imm2 in a memory specified with the addr6

TST

[addr6],imm2

...Tests a bit specified with the imm2 in a memory specified with the addr6

Write only or read only control bits may have been assigned depending on the peripheral circuit. Pay attention when using the above-mentioned instructions for such bits or addresses containing such bits.

•Signed 8-bit PC relative addressing

The signed 8-bit PC relative addressing is the addressing mode used for the branch instructions. The signed 8-bit relative address (-128 to 127) that is specified in the operand is added to the address next to the branch instruction to branch to that address.

The following instructions operate in this addressing mode.

Jump instructions:

JR

sign8

 

JRC

sign8

 

JRNC

sign8

 

JRZ

sign8

 

JRNZ

sign8

Call instruction:

CALR

sign8

4.1.2 Extended addressing mode

In the S1C63000, when data is written to the EXT register (the E flag is set) and a specific instruction follows, the data specified by that instruction is extended with the EXT register data (see Section 2.1.5). When the E flag is set, instructions are extended in an addressing mode different from the mode that is specified in each instruction. This is the extended addressing mode that will be explained below. However, instructions that can operate in the extended addressing mode are limited to those indicated in the instruction list, so check it when programming.

Further the extended addressing mode is effective only for the instruction following immediately after writing data to the EXT register and setting the E flag to "1" (the E flag is reset to "0" by executing that instruction). When using an instruction in the extended addressing mode, write data to be extended to the EXT register or set the E flag (when the E register has already been set).

•16-bit immediate data addressing

The addressing mode of the following instructions, which have an 8-bit immediate data as the operand, change to the 16-bit immediate data addressing when the E flag is set to "1". Consequently, it is possible to transfer and operate a 16-bit immediate data to the X or Y register.

Instructions that operate in the 16-bit immediate data addressing mode with the E flag

LDB

%XL,imm8

LDB

%Y,imm8

ADD

%X,sign8

ADD

%Y,sign8

CMP

%X,imm8

CMP

%X,imm8

The data is extended into 16 bits in which the E register data is the high-order 8 bits and the immediate data specified with the above instruction is the low-order 8 bit.

S1C63000 CORE CPU MANUAL

EPSON

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