HP KAYAK XU800 manuals
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140 pages 4.5 Mb
2 NoticeThe information contained in this document is subject to change without notice Adaptec® is a registered trademark of Adaptec, Inc WOLTM (Wake on LAN) is a trademark of IBM Hewlett-PackardFrance Business Desktop Division (BDD) Outbound Marketing Communications 38053 Grenoble Cedex France 3 Contents1 System Overview 4 2 System BoardThe Input/Output Controller Hub (82801AA) 5 3 Interface Cards4 Mass Storage Devices 5 HP BIOS 6 6 Tests and Error MessagesMaxiLife Test Sequence and Error Messages 7 Connectors and Sockets 7 PrefaceConventions 8 BibliographyOnline documentation can be obtained from the HP World Wide Web site: www.hp.com/go/kayaksupport Troubleshooting Guide ❒HP Kayak XU800 PC Workstation Technical Notes — English only ❒HP Kayak XU800 PC Workstation Service Handbook Chapter — English only ❒Image Creation and Recovery CD-ROM — ❒ ELSA GLoria Synergy graphics card Be Obtained At: http://www.elsa.com ❒ Matrox graphics cards http://www.matrox.com ❒ 3D Labs Oxygen GVX1 graphics card http://www.3dlabs.com ❒ Intel Chipsets. Intel I840 chipset http://developer.intel.com ❒ Intel Pentium III Processor 9 System Overview10 1 System OverviewHP Kayak XU800 PC Workstation Overview HP MaxiLife Utility and a LCD status panel Operating System All models are preloaded with Windows NT® 4.0 SP5 Main Memory Models include either: Maximum amount of memory that can be installed is: memory installed in pairs 2 GB (4 x 512 MB) 512 MB RDRAM ECC modules ECC main memory 512 MB unbuffered 100 MHz ECC SDRAM modules Mass Storage Seven shelves supporting: one free) (height 1”); 5¼-inchshelves • Two internal 3½-inchhard disk drives (height 1.0”) SCSI Controller Ultra 160 SCSI controller: (internal + external) devices that can be connected IDE Controller four IDE devices 11 Video ControllersSGRAM video memory (maximum configuration) Matrox® Millennium G250 AGP video controller with 16 MB SGRAM video memory (maximum configuration) ration) All models have: performance graphics interface • Three 32-bit33 MHz PCI1 slots: 1, 2 and 5 (5 V) • Two 64-bit66 MHz PCI slots: 3 and 4 (3.3 V) LAN Card Specification CD-ROMDrive Audio (CS4297) audio HP UltraFlow Cooling System Alert reporting to MaxiLife and TopTools 13 Front and Side Views14 Rear View15 Front PanelThe front panel of HP Kayak XU800 PC Workstation has the following features: The front panel of has the following features: Liquid Crystal Display •On/Off LED. There are five states: Blank. Indicates that the computer is turned off Red flashing Amber Hard disk drive activity LED Activated during POST and when the hard disk drive is being accessed 16 Physical CharacteristicsElectrical Specifications 17 Power Consumption and Cooling18 Environmental Specifications19 Power Saving and Ergonometry•No sleeping state: Windows NT 4 (Full On and Off) •APM: Windows 95 and Windows 98 SE APM (Full On, Standby, Suspend and Off) ACPI Windows 98 SE Windows NT 20 Power Saving and Ergonometry for APM SystemsPower Saving Modes and Resume Events for ACPI Systems 21 Power-Onfrom Space-BarSoft Power Down 22 DocumentationTitle Paper-based (see address below) Access HP World Wide Web Site http://www.hp.com/go/kayaksupport then select HP Kayak XU800 PC Workstation 23 Where to Find the Information27 System Board28 2 System BoardSystem Board Overview System Board Overview 29 Architectural ViewArchitectural View 30 Universal AGP Pro Slot31 PCI Slots32 PCI SlotPCI 32-bit/33MHz Bus PCI 64-bit/66MHz Bus Hub), USB ports and IDE buses Digital audio CS4280 controller Onboard AIC7892 SCSI U160 controller 33 Switch BoxesSystem Board Switches Switch Default Function: UP1 There are two types of system board switch boxes that may be used on the HP Kayak XU800 PC Workstation 34 ChipsetAGP 4x (graphic) bus, Hub Link 8-bitand Hub Link 16-bit,and the 35 Memory Controller Hub (8240)36 The following table shows the features that are available in the MCH HostBridge/Controller Processor/Host Bus: • Accelerated Graphics Port (AGP) Interface: ❒ Single Universal AGP PRO connector MHz Host Bus frequency 2x/4x Fast Write protocol up to two processors low AGP 2.0 3.3 V or 1.5 V signalling snooped receivers for reduced power) ❒ Support for 36-bithost bus address ❒ Hierarchical PCI configuration mechanism Parity errors generate SERR cannot be serviced immediately Memory Controller Direct Rambus: SDRAM: Hubs for SDRAM (MRH-S) Supporting 300 MHz or 400 MHz Currently, two MRH-Sdevices are supported ❒ RDRAM 64 Mb, 128 Mb, 256 Mb devices bandwidth technology cost and upgrade path ❒ Unbuffered DIMMs are supported — 512 MB using 64 Mb DRAM technology ❒ Up to 4 rows or 2 DS DIMMs per MRH-S — 1 GB using 128 Mb DRAM technology ❒ Up to 8 simultaneous open pages: — 2 GB using 256 Mb DRAM technology 256 Mbit SDRAM devices Mbit RDRAM devices ❒ Configurable optional ECC operation: Detection (scrubbing) • Hub Link 8-bitInterface to ICH: • Hub Link 16-bitInterface to P64H: (266 MB/sec) (533 MB/sec) 37 MCH Interface38 Accelerated Graphics Port (AGP) Bus InterfaceAGP 4x Bus 39 Main Memory Controller40 Dual Rambus BusThe Dual Rambus bus is comprised of 16 x 2 bits of data information, and 41 Memory Expansion Card Connectorpairs pairs Each RIMM socket is connected to the SMBus and is described on page 42 Each DIMM socket is connected to the SMBus and is described on page43 Read/Write BuffersSystem Clocking synthesizer (which produces reference clocks for the host, AGP and PCI interfaces) I/O APIC I/O APIC is used to support dual processors as well as enhanced interrupt the ICH is used in conjunction with a second I/O APIC controller in the P64H 44 PCI 64-bitHub64-bit66 MHz bus 45 PCI 64-bit66 MHz Bus Interface46 Devices Supported on the PCI 64-bit66 MHz BusThe following devices are supported on the PCI 64-bit66 MHz bus Ultra-Wide160 SCSI Controller PCI slots are explained in detail on page 47 SelectSCSI User’s Guide 48 The Input/Output Controller Hub (82801AA)49 The following table shows the available ICH features50 ICH Architecturereceive the adequate bandwidths bandwidth necessary for peak performance ICH PCI Bus Interface The ICH PCI provides the interface to a PCI bus interface operating at 33 MHz. This interface implementation is compliant with PCI Rev Specification, supporting up to six external PCI masters in addition to the rate of 133 MBytes/sec. The maximum PCI burst transfer can be between 256 bytes and 4 KB. It also supports advanced snooping for PCI master bursting, and provides a pre-fetchmechanism dedicated for IDE read Refer to the table page 68for ICH interrupts SMBus Controller maximum of (100 kHz). The SMBus Host interface allows the processor to external masters to activate power management events. The bus connects board, both during system boot and run-time for information on the MaxiLife ASIC The ICH implements the LPC interface 1.0 specification The USB (Universal Serial Bus) controller provides enhanced support for supports two stacked connectors on the back panel. These ports are built into the ICH, as standard USB ports The ICH is USB revision 1.1 compliant program. Currently, only the Microsoft Windows 95 and Windows operating systems provide support for the USB 51 AC’97 ControllerPC Workstation uses the dedicated dual chip PCI solution of the CS4280 audio controller and the CS4297 Codec Audio Codec ‘97 (AC’97) Refer to page 54for information about the CS4280 and CS4297 audio solution IDE Controller The IDE controller is implemented as part of the ICH chip and has PCI two connectors per channel. Two IDE devices (one master and one slave) Ultra-ATAcables must be used for Ultra-ATAmodes (Ultra-ATA/33and Ultra-ATA/66) rates of up to 66 Mbytes/sec are supported. The IDE controller integrates 16 x 32-bitbuffers for optimal transfers device. The BIOS automatically determines the fastest configuration that each device supports DMA Controller The seven-channelDMA controller incorporates the functionality of two 82C37 DMA controllers. Channels 0 to 3 are for 8-bit count-by-byte as a generic bus master request Interrupt Controller controllers. The two interrupt controllers are cascaded so that 14 external and two internal interrupts are possible. In addition, the ICH supports a on page 68shows how the master and slave controllers are connected 52 Timer/Counter BlockReal Time Clock Enhanced Power Management 53 Devices on the PCI 32-bit33 MHz Bus54 Dual Chip PCI Audio Solution55 Devices on the SMBus57 ICH SMBus Masterthe SMBus is done through the ICH SMBus interface. Typically, the processor has access to all the devices connected to the SMBus DIMM Sockets used to store data online RIMM Sockets ADM1024 The ADM1024 chip is a hardware monitoring sensor dedicated to the processor temperature. This chip uses the thermal diodes integrated into through the SMBus. It also monitors processor power supply voltages Serial EEPROM memory (in the event of battery failure).When installing a new system PC Workstation. The computer uses 16KBytes of Serial EEPROM a time can be returned to its unprogrammed state by the application of appropriate electrical signals. In effect, it can be made to behave like very slow, non-volatileRAM. It is used for storing the tatoo string, the serial number, and the parameter settings for the Setup program as well as MaxiLife firmware LM75 Temperature Sensor The sensor is used to measure the temperature in various areas of the system board. This information is used to regulate fans 59 MaxiLife Architecturepower cord is plugged in 60 Devices on the Low Pin Count Bus61 The Super I/O Controller (NS 87364)62 FirmWare Hub (82802AB)The following table shows the available FWH features 64 Host BusThe supported operating frequencies of the GTL+ bus are 100 MHz or 65 Intel Pentium III ProcessorOptional Second Processor 66 particular switch settings are requiredUpgrading a single processor to a dual processor system on Windows NT and Windows 2000 platforms is made easier with the HP DualExpress application which is included in the HP processor application kit Installing a second processor is only advantageous when the software can best use of the Pentium III 32-bitarchitecture (though other operating The two processors must have the same speed Configuring for HP Kayak XU800 PC Workstations support Symmetric Multi-Processing HP Kayak XU800 PC Workstations Multi-Processing (SMP). When a second processor is added, it is automatically detected so there is no specific configuration required The “mono-processing”mode has been implemented in order to support details Processor Clock clock is derived from the Host Bus by applying a “fix ratio” Bus Frequencies internal clock multiplier within the processor The bus frequency and the processor voltage are set automatically 67 Cache Memory68 Input/Output Controller Hub InterruptsPCI 64-bitHub Interrupts Interrupt Controllers 69 Interrupt SourceThere are three major interrupt modes available: PIC mode: 70 PCI Interrupt Request Lines71 Interface Cards87 Mass Storage Devices91 HP BIOS92 Using the HP Setup Program93 Integrated USB InterfaceAuto Integrated I/O Ports Integrated SCSI Security Administrator Password User Password •Power-onPassword. If enabled, a password will be requested on boot Start from Floppy and Hardware Protection 94 Boot MenuBoot Device Priority Power Menu 95 Updating the System BIOSthen select HP Kayak XU800 PC Workstation Restoring BIOS Default Settings 2Press to load the default settings from the Setup program 3Set the “Reset Configuration Data” to Yes in the Main menu 96 Clearing the CMOSClearing the CMOS 2Set the system board switch 4 to the DOWN position to clear the CMOS memory 3Replace the cover, and only reconnect the power cord “Configuration has been cleared You can now: Replace the cover Switch on the PC Workstation and allow it to startup Setup.” 5Turn off the PC Workstation, disconnect the power cord, and remove the cover 6Set the system board switch 4 to the UP position to retain the configuration 7Replace the cover, and reconnect the power cord and data cables Switch on the PC Workstation. Run the 9Press to save the configuration and exit from the Setup program 97 Clearing Passwords2Set the system board switch 3 to the UP position to clear passwords 98 Recovering the BIOS (Crisis Mode)99 Adaptec SCSISelect Configuration UtilityDefault Settings 100 drives > 1 GBytedisk drives of more than 1 GByte Verbose/Silent Mode Host Adapter BIOS Controls the state of the BIOS at POST BIOS as Fixed Disks Displays BIOS Initialization Enables booting from a CD-ROM Domain Validation integrity of data transmission SCSI Device Configuration Options SCSI Device Options SyncTransfer Rate Enable Disconnection to as Disconnect/Reconnect) Initiate Wide Negotiation (16-bitadapters only) 16-bitSCSI device Send Start unit Command Unit command to the SCSI bus Enable Write Back Cache back cache in the hard disk drive BIOS Multiple Lun Support Include in BIOS Scan device driver software 101 Starting the SCSISelect Configuration Utility102 System Memory Map103 HP I/O Port Map (I/O Addresses Used by the System1)104 DMA Channel Controllers105 IRQs Used by the PC Workstation107 Tests and Error Messages108 Basic Pre-bootDiagnostics109 Post Test Sequence and Post Error110 Operating System Boot Phase111 Run-TimeErrors112 Main Menu113 Diagnosticstests are displayed on the LCD status panel, one after another, when the LCD buttons are pressed OK or FAIL 114 Typical Diag ErrorMessages For More Information Refer to the online Troubleshooting Guide for more information about this About MaxiLife diagnostics utility at the HP World Wide Web site: http://www.hp.com/go/kayaksupport 115 Order in Which POST Tests Are Performeddetails, press to get the HP Summary Screen For example, if the error 0101 - 52 is displayed A table listing the error codes, causes and symptoms is on page 116 POST Routine DescriptionUncompressed Initialization Codes verified memory refresh, and entering 4 GB flat mode Starting Memory sizing the system BIOS checksum go to checkpoint code E0h Otherwise, going to checkpoint code D7h Passing control to the interface module Main system BIOS runtime code will be decompressed Passing control to the main system BIOS in shadow RAM Bootblock Recovery Codes memory test Initializing the interrupt vector table Initializing the DMA and Interrupt controllers 117 POST Routine Description (Continued)Initializing the floppy disk drive A read error occurred while reading the floppy disk drive A: Searching for the AMIBOOT.ROM file for the root directory AMIBOOT.ROM file is not found in the root directory file Reading the AMIBOOT.ROM file, cluster by cluster AMIBOOT file is not the correct size Disabling internal cache memory Detecting the type of flash ROM Erasing the flash BIOS Programming the flash BIOS Disable Non-MaskableInterrupt (NMI) BIOS stack has been built. Next, disabling cache memory Uncompressing the POST code Initializing processor and the processor data area CMOS checksum calculation performed controller 118 Keyboard command byte is then writtenIssuing the Pin 23 and 24 blocking and unblocking commands AMIBCP or the <End> key was pressed 8254 timer initialization Initializing memory refresh test initialization the interrupt vectors vector initialization begins Clearing the password if the POST DIAG switch is on Setting video mode System bus initialization, static, output devices, if present Video ROM performs any required configuration before testing ROM is searched, then control passed on to it the video 119 checkingVideo display checking is complete. Setting the display mode Display mode is set. Displaying the display mode text Initializing the bus input, IPL, and if present and general devices Displaying the bus initialization errors Preparing the descriptor tables around at 0:0 size 640 KB memory memory above 1 MB checkpoint 4Eh checkpoint 52h memory size 120 for relocation and shadowingabove 1 MB and the NMI on relocation and shadowing message DMA and Interrupt controller test test Test extended memory address lines Extended NMI source enabling is in progress the keyboard reset command command the circular buffer locked key 121 Code85h bypassing WINBIOS Setup 86h 87h code and executing the AMIBIOS Setup or WINBIOS Setup utility 88h programming after WINBIOS Setup 89h 8Bh 8Ch Programming the WINBIOS Setup options 8Dh 8Fh 91h 95h Initializing the bus option ROMs from C800 96h Initializing before passing control to the adaptor ROM at C800 97h is then checked 98h required processing after the option ROM returned control 99h data area and printer bas address 9Ah 9Bh before the co-processortest 9Ch 9Dh 9Eh and Num Lock key. Issuing the keyboard ID command 122 Displaying any soft key errorsNMI adaptor ROM at E000h Initialization before passing control to the adaptor ROM at E000h the E000h option ROM had control Building the multi-processortable, if necessary Uncompressing the DMI table data and initializing DMI POST System configuration is displayed Copying any code to specific areas 123 Error Message SummaryError Message Summary 0070 CPU Terminator Card Error Press <Enter> to view more information about error1 <F1= Continue Category #2: WARNING 00100 Keyboard Warning1 Category #3: If the error is serious, the POST should prompt: Press <Enter> to view more information about error <F1= Continue>, <F2= Fix 127 Beep Codes129 load the default BIOS settingshow to update the BIOS The CMOS RAM has failed Replace the processor(s) 131 Connectors and Sockets132 VRMVRM 133 SCSI ConnectorsSCSI Connector Additional SCSI LED Additional SCSI LED Connector (4-pin) 134 Aux Power ConnectorPower Supply Connector for System Board (20-pin) Aux. Power Connector Wake On LAN Wake On LAN (WOL) Rear Fan Connector Fan Connector 135 PCI FanStatus Panel and Intrusion Intrusion Hard Disk Drive Temperature Connector HDD Temperature 136 VGA DB15 ConnectorVGA DB Connector Pins Standard VGA DDC2B LCD Panel LCD Panel Ethernet UTP Connector 137 Rear Panel Socket Pin LayoutsRear Panel Socket Pin Layouts Keyboard (left) and Mouse (right) Keyboard and Mouse Connectors Data Not Used +5 V dc Clock 138 USB Stacked ConnectorUSB Stacked Connector Serial Port A (top) and Serial Port B (bottom) 9-pinSerial Port Connector 139 25-pinParallel ConnectorMIDI/Joystick 25-pinParallel Connector MIDI/Joystick Connector External Audio Jacks
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