HP KAYAK XU800 Host Bus, The supported operating frequencies of the GTL+ bus are 100 MHz or

2 System Board

Host Bus

Host Bus

The Host bus of the Pentium III processors, also referred to as the FSB (Front Side Bus), is implemented in the GTL (Gunning Transceiver Logic)+ technology. This technology features open-drain signal drivers that are pulled-up to 1.5 V through resistors at bus extremities; these resistors also act as bus terminators, and are integrated in the processor.

If only one processor is installed, a terminating board must be installed in the second processor slot.

				Intel Pentium III
	Intel Pentium III
				Processor
		Processor						SECC-2 cartridge
	with L2 cache memory			(optional second processor)
SECC-2 cartridge				with L2 cache memory
Address (36)
							Host (also called FSB)
Control
							Bus 100/133 MHz,
Data (64)							1 GB/sec data trans-
							fer rate)
			I840
				Dual Rambus Bus		Memory
	AGP 4x Bus		Memory
					Expansion Card
			Controller Hub
					Connector
		HUB	(MCH)
		LINK 16	82840-QP

HUB LINK 8

I/O Controller

Hub

(ICH) 82801AA

The supported operating frequencies of the GTL+ bus are 100 MHz or

133 MHz. The width of the data bus is 64 bits, while the width of the address is 36 bits. Along with the operating frequencies, the processor voltage is set automatically.

The control signals of the Host bus allow the implementation of a “split - transaction” bus protocol. This allows the Pentium III processor to send its request (for example, for the contents of a given memory address) and then to release the bus, rather than waiting for the result, thereby allowing it to

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