2 System Board

Memory Controller Hub (8240)

The following table shows the features that are available in the MCH HostBridge/Controller.

 

Feature

 

Feature

 

 

 

 

•

Processor/Host Bus:

 

• Accelerated Graphics Port (AGP) Interface:

 

❒ Supports up to two Pentium III processors at: 100 MHz/133

 

❒ Single Universal AGP PRO connector.

 

MHz Host Bus frequency.

 

❒ AGP Rev 2.0 compliant, including AGP 4x data transfers and

 

❒ Supports full Symmetric Multiprocessor (SMP) Protocol for

 

2x/4x Fast Write protocol.

 

up to two processors.

 

❒ AGP Universal Connector support via dual mode buffers to al-

 

❒ Provides an 8-deep In-Order Queue supporting up to eight

 

low AGP 2.0 3.3 V or 1.5 V signalling.

 

outstanding transaction requests on the host bus.

 

❒ AGP PIPE# or SBA initiated accesses to DRAM is not

 

❒ Desktop optimized GTL+ bus driver technology (gated GTL+

 

snooped

 

receivers for reduced power).

 

❒ AGP FRAME initiated accesses to DRAM are snooped

 

❒ Support for 36-bit host bus address.

 

(snooper identifies that data is coherent in cache memory).

 

❒ IERR and BERR signals generate SCi/SERR.

 

❒ Hierarchical PCI configuration mechanism.

 

❒ Parity protection on address and resource signals:

 

❒ Delayed transaction support for AGP-to-DRAM reads that

 

Parity errors generate SERR.

 

cannot be serviced immediately.

 

 

 

 

•

Memory Controller.

 

 

Direct Rambus:

 

SDRAM:

 

 

❒ Dual Direct Rambus Channels operating in lock-step (both

 

❒ Up to 8 GB of SDRAM using four external Memory Repeater

 

channels must be populated with a memory module).

 

Hubs for SDRAM (MRH-S).

 

Supporting 300 MHz or 400 MHz.

 

Currently, two MRH-S devices are supported.

 

❒ RDRAM 64 Mb, 128 Mb, 256 Mb devices.

 

❒ Interleaved 100 MHz support using 4 MRH-S for a maximum

 

❒ Minimum upgrade increment of 16 MB using 64 Mb DRAM

 

bandwidth.

 

technology.

 

❒ Non-Interleaved 100 MHz support using 2 MRH-s for lower

 

❒ Up to 64 Direct Rambus devices (without using MRH-R).

 

cost and upgrade path.

 

Dual channel maximum memory array size is:

 

❒ Unbuffered DIMMs are supported.

 

— 512 MB using 64 Mb DRAM technology.

 

❒ Up to 4 rows or 2 DS DIMMs per MRH-S.

 

— 1 GB using 128 Mb DRAM technology.

 

❒ Up to 8 simultaneous open pages:

 

— 2 GB using 256 Mb DRAM technology.

 

— 2 KByte page size support for 64 Mbit SDRAM devices.

 

❒ Up to 8 simultaneous open pages:

 

— 4 KByte - 16 KByte page sizes supporting 64 MBit to

 

— 1 KByte page size support for 64 Mbit, 128 Mbit and 256

 

256 Mbit SDRAM devices.

 

Mbit RDRAM devices.

 

❒ Configurable optional ECC operation:

 

— KByte page size support for 256 Mbit RDRAM devices.

 

— ECC with single bit Error Correction and multiple bit Error

 

 

 

Detection.

 

 

 

— Single bit errors corrected and written back to memory

 

 

 

(scrubbing).

 

 

 

• Hub Link 8-bit Interface to ICH:

 

• Hub Link 16-bit Interface to P64H:

 

❒ High-speed interconnect between the MCH and ICH

 

❒ High-speed interconnect between the MCH and P64H

 

(266 MB/sec).

 

(533 MB/sec).

 

 

 

 

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