HP KAYAK XU800 MCH Interface, Rambus bus and AGP 4x bus, P64H for transfers between the processor(s) on the Host bus (FSB), Dual

2 System Board

Memory Controller Hub (8240)

Feature		Feature
• Power management:	•	Arbitration:
❒ SMRAM space re-mapping to A0000h - BFFFFh (128 KB).		❒ Distributed Arbitration Model for Optimum Concurrency
❒ Extended SMRAM space above 256 MB, additional 128 K,		Support.
256 K, 512 K, 1 MB TSEG from Top of Memory, cacheable		❒ Concurrent operations of host, hub interface, AGP and
(cacheability controlled by processor).		memory buses supported via a dedicated arbitration and
❒ Suspend to RAM.		data buffering logic.
❒ ACPI Rev. 1.0 compliant power management.
❒ APM Rev. 1.2 compliant power management.
❒ Power-managed states are supported for up to two
processors.
• 544 mBGA MCH package.	•	Input/Output Device Support:
		❒ Input/Output Controller Hub (ICH).
		❒ PCI 64 Hub (P64H).

MCH Interface

The MCH interface provides bus control signals and address paths via the

Hub Link 8-bit access to the ICH and via the Hub Link 16-bit access to the

P64H for transfers between the processor(s) on the Host bus (FSB), Dual

Rambus bus and AGP 4x bus.

The MCH supports 36-bit host addresses, allowing the processor to address a space of 64 GB. It also provides an 8-deep In-Order Queue supporting up to eight outstanding transaction requests on the host bus.

Host-initiated input/output signals are positively decoded to AGP, Hub Link 16-bit interface, or MCH configuration space and subtractively decoded to Hub Link 8-bit interface. Host-initiated memory cycles are positively decoded to AGP, Hub Link 16-bit interface, or DRAM, and are again subtractively decoded to Hub Link 8-bit interface.

AGP semantic memory accesses initiated from AGP to DRAM do not require a snoop cycle (not snooped) on the Host bus, since the coherency of data for that particular memory range will be maintained by the software. However, memory accesses initiated from AGP using PCI Semantics and accesses from either Hub Link interface (8-bit or 16-bit) to DRAM do require a snoop cycle on the Host bus.

Memory access whose addresses are within the AGP aperture are translated using the AGP address translation table, regardless of the originating interface.

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