HP KAYAK XU800 manual Following table shows the available ICH features

7 a• J½p

The Input/Output Controller Hub (82801AA)

The following table shows the available ICH features.

	Otp		Otpt
•	Multi-function PCI Bus Interface:	•	Enhanced DMA Controller:
	❒ PCI at 32-bit 33 MHz.		❒ Two 82C37 DMA controllers.
	❒ PCI Rev 2.2 Specification.		❒ PCI DMA with 2 PC/PCI Channels in pairs.
	❒ 133 Mbyte/sec data transfer rate.		❒ LPC DMA.
	❒ Master PCI Device Support for up to six devices.		❒ DMA Collection Buffer to provide Type-F DMA performance
			for all DMA channels.
•	USB, supporting:	•	Interrupt Controller:
	❒ USB revision 1.1 compliant.		❒ Two cascaded 82C59 controllers.
	❒ UHCI Implementation with Two USB Ports for serial		❒ Integrated I/O APIC capability.
	transfers at12 or 1.5 Mbit/sec.		❒ 15 Interrupt support in 8259 Mode, 24 supported in I/O APIC
	❒ Wake-up from sleeping states (refer to table on page 19).		mode.
	❒ Legacy keyboard/mouse software.		❒ Serial Interrupt Protocol.
•	Power Management Logic:	•	Integrated IDE Controller:
	❒ ACPI 1.0 compliant.		❒ Independent Timing of up to four drives.
	❒ Support for APM-based legacy power management for non-		❒ Ultra ATA/66 Mode (66 Mbytes/sec).
	ACPI implementations.		❒ Ultra ATA/33 Mode (33 Mbytes/sec).
	❒ ACPI defined power states (S1, S3, S4, S5).		❒ PIO Mode 4 transfers up to 14 Mbytes/sec.
	❒ ACPI power management timer.		❒ Separate IDE connections for Primary and Secondary cables.
	❒ SMI generation.		❒ Integrated 16 x 32-bit buffer for IDE PCI Burst transfers.
	❒ All registers readable/restorable for proper resume from 0 V		❒ Write Ping-Pong Buffer for faster write performances.
	suspend states.
	❒ PCI PME#.
•	Real-Time Clock, supporting:	• System TCO Reduction Circuits:
	❒ 256-byte battery-backed CMOS RAM.		❒ Timers to Generate SMI# and Reset Upon.
	❒ Hardware implementation to indicate Century Rollover.		❒ Timers to Detect Improper Processor Reset.
			❒ Integrated Processor Frequency Strap Logic.
• Timers Based on 82C54:		•	SMBus
	❒ System Timer, Refresh Request, Speaker Tone Output.		❒ Host Interface allows processor to communicate via SMBus.
			❒ Compatible with 2-wire I2C bus.
• System Timer, Refresh Request, Speaker Tone Output.		•	GPIO:
			❒ TTL, Open-Drain, Inversion.
• Firmware Hub (FWH) interface.		• 3.3 V operation with 5 V Tolerant Buffers for IDE and PCI signals.
•	241 BGA Package.	•	Alert-On-LAN (AOL) support.

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