HP KAYAK XU800 manual QWh2 R, QWh C R

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Memory Controller Hub (8240)

Write accesses from Hub Link interface (8-bit or 16-bit) to the AGP are supported.

The MCH can support one or two Pentium III processors, at FSB frequencies of 100/133 MHz using GTL+ signalling. Refer to page 64 for a description of the Host bus.

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A controller for the Universal AGP (Accelerated Graphics Port) Pro slot is integrated in the MCH. The AGP Bus interface is compatible with the Accelerated Graphics Port Specification, Rev 2.0, operating at 133 MHz, and supporting up to 1 GB/sec data transfer rates. The MCH supports only a synchronous AGP interface, coupling to the Host bus frequency.

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The AGP bus is a dedicated bus for the graphics subsystem, which meets the needs of high quality 3D graphics applications. It has a direct link to the

MCH

The AGP bus is based upon a 66 MHz, 32-bit PCI bus architecture, to which several signal groups have been added to provide AGP-specific control and transfer mechanisms.

AGP specific transactions always use pipelining. This control mechanism increases the bus efficiency for data transfer. Sideband Addressing (SBA) may also be used by AGP transaction requests which further increases the bus efficiency for data transfer. The supported modes are detailed below:

•FRAME based AGP. Only the PCI semantics are: 66 MHz, 32-bit, 3.3 V, 266 MB/s peak transfer rate.

•AGP 1X with pipelining, sideband addressing can be added: uses 66 MHz, 32-bit, 3.3 V, increased bus efficiency, 266 MB/s peak transfer rate.

•AGP 2X with pipelining, sideband addressing can be added: 66 MHz double clocked, 32-bit, 3.3 V, 533 MB/s peak transfer rate.

•AGP 4X with pipelining, sideband addressing can be added: 133 MHz double clocked, 32-bit, 1.5 V, increased bus efficiency, 1066 MB/s peak transfer rate

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