7 a• J½p
Memory Controller Hub (8240)
‘tps4ex Juut | The MCH defines a data buffering scheme to support the required level of |
| concurrent operations and provide adequate sustained bandwidth between |
| the DRAM subsystem and all other system interfaces (CPU, AGP and PCI). |
a½rzx”v | The MCH operates the host interface at 100 MHz or 133 MHz, PCI at 33 MHz |
| and AGP at 66/133 MHz. Coupling between all interfaces and internal logic is |
| done in a synchronous manner. The clocking scheme uses an external clock |
| synthesizer (which produces reference clocks for the host, AGP and PCI |
| interfaces). |
Q4W IXQK | I/O APIC is used to support dual processors as well as enhanced interrupt |
| processing in the single processor environment. The I/O APIC controller of |
| the ICH is used in conjunction with a second I/O APIC controller in the |
| P64H. |
43
