7 a• J½p

Memory Controller Hub (8240)

e SGAC92

The MCH Host Bridge/Controller is contained in a 544-pin Ball Grid Array (BGA) package and is the bridge between the Host bus, Dual Rambus bus (main memory), AGP 4x (graphic) bus, Hub Link 8-bit and Hub Link 16-bit.

The following figure shows an example of the system block diagram using the MCH.

 

 

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HP KAYAK XU800 manual SGAC92, Memory Controller Hub