HP KAYAK XU800 manual SGAC92, Memory Controller Hub

7 a• J½p

Memory Controller Hub (8240)

e SGAC92

The MCH Host Bridge/Controller is contained in a 544-pin Ball Grid Array (BGA) package and is the bridge between the Host bus, Dual Rambus bus (main memory), AGP 4x (graphic) bus, Hub Link 8-bit and Hub Link 16-bit.

The following figure shows an example of the system block diagram using the MCH.

		Q”t“ Xt”x• QQQ			Q”t”• QQQ
					Xrt
		X½rt½
				-½¼x½”p“ tr½”s ¼½rt½
		x rprwt •t•½
aMKK27 rpvt					x T7 rprwt •t•½
	Isst8<.
	K½”½“
	Lp.
				Q>95 Ut•½
		IOX 9 J	K½”““t Pq -UKP.
				>7>952YX
	c”x“	-688 UP OJ UJ4
			IOX		Lp“ ‘p•q J
	IOX	sp p”ut p.		Ut•½
	X‘W	Q”tuprt		K½”““t	-739 OJ4 p 855 UP
		PcJ
	K½””tr				837 OJ4p 955 UP
		TQVS 6<
					sp ut t.
		-:88 UJ4 spp
		.
XKQ J<92qx1 << UP		X<9P		PcJ TQVS >
:88 UJ4p p”t t
		XKQ		-7<< UJ4 spp
				t.
		Q”tprt
W”q½p IQK=>A7	a“½ 8 2 <92qx4<< UP
aKaQ c6<5			Q4W K½”½““t Pq
K½”““t
	a“½ 9 2 <92qx4<< UP			-QKP. >7>56II

aMKK27 rpsvt

P½ -p“ rp““ts NaJ. J 6554688 UP 6 OJ4tr spp p”t t.

Ut•½

M¼p”

K½””tr½

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