Intel IXP45X manuals

108 pages1.67 Mb

2HDD February 2007 2Document Number: 305261, Revision: 004
3Contents
- 5Figures
- 6Tables
7Revision History
91.0 Introduction
- 1.1 Content Overview
- 101.2 Related Documentation
- 111.3 Acronyms and Abbreviations
- 1.4 Overview
  - December 2006 HDD Document Number: 305261; Revision: 004 13
  - IntroductionIntel IXP45X and Intel IXP46X Product Line of Network Processors
    - APB 66.66 MHz x 32 Bits
    - Master on North AHB
    - Master on South AHB
  - 13Figure 1. Intel IXP465 Component Block Diagram
    - 16 GPIO
    - HSS 0 HSS 1 UTOPIA 2/MII/SMII MII/SMII MII/SMII
    - 32 Bit + ECC MPI 133 MHz x 64
      - South AHB 133.32 MHz x 32 bits
      - North AHB 133.32 MHz x 32 bits
    - Cryptography Unit
      - 32 bit at 33/66 MHz8/16/32 bit + Parity Bus Arbiters
      - Slave Only AHB Slave / APB Master
- 141.5 Typical Applications
152.0 System Architecture
- 2.1 System Architecture Description
- 2.2 System Memory Map
  - Intel IXP45X and Intel IXP46X Product Line of Network ProcessorsSystem Architectur e
  - 16Intel
    - HDD February 2007 16 Document Number: 305261; Revision: 004
    - Figure 2. Intel IXP465 Example System Block Diagram
      - I2C
      - JTAG Header
        cPCI Bus
  - IXP46X Product Line of Network Processors
173.0 General Hardware Design Considerations
- 3.1 Soft Fusible Features
- 183.2 DDR-266 SDRAM Interface
  - 3.2.1 Signal Interface
    - 19Table 4. DDR SDRAM Interface Pin Description (She et 2 of 2)
  - 3.2.2 DDR SDRAM Memory Interface
  - 3.2.3 DDR SDRAM Initialization
- 203.3 Expansion Bus
  - 213.3.1 Signal Inte rface
  - 3.3.2 Reset Conf igu ration Straps
  - 233.3.3 8-Bit Device Interface
  - 3.3.4 16-Bit Device Interface
  - 243.3.5 32-Bit Device Interface
258-Bit Device
16-Bit Device
32-Bit Device
- Figure 4. 8/16/32-Bit Device Interface: Byte Enable
268-Bit Device
- Byte Access
16-Bit Device
- 16-Bit-W ord Access
32-Bit Device
- 32-Bit-W ord Access
- Product Line of
- 3.3.6 Flash Interface
  - Intel
2716-Bit Device
- 16-Bit- Word A ccess
Flash
Intel
- IXP46X Product Line of Network Processo r s
- 3.3.7 SRAM Interface
- 3.3.8 Design Notes
- 3.4 UART Interface
- 288-Bit Device
  - Byte Access
  - Intel IXP46X Product Line of Network Pro cessor s
  - 293.4.1 Signal Inte rface
  - 303.5 MII/SMII Interface
    - 313.5.1 Signal Inte rface MII
      - Table 8. MII NPE A Signal Recommendations
      - Table 9. MII NPE B Signal Recommendations (Sheet 1 of 2)
      - 32Table 10. MII NPE C Signal Recommendations
      - Table 9. MII NPE B Signal Recommendations (Sheet 2 of 2)
    - 333.5.2 Device Connection, MII
      - Table 11. MAC Management Signal Recommendations NPE A,B,C
      - Figure 8. MII Interface Example
    - 343.5.3 Signal Interface, SMII
    - 3.5.4 Device Connection, SMII
  - 353.6 GPIO Interface
    - 363.6.1 Signal Interface
    - 3.6.2 Design Notes
  - 373.7 I2C Interface
    - 3.7.1 Signal Inte rface
    - 3.7.2 Device Connection
  - 383.8 USB Interface
    - 393.8.1 Signal Interface
    - 3.8.2 Device Connection
      - Figure 11. U SB Host Down Stream Interface Example
40Host Device
- 3.9 UTOPIA Level 2 Interface
- 41Device Host
  - 423.9.1 Signal Interface
  - 3.9.2 Device Connection
    - Table 16. UTOPIA Signal Recommendations
  - 433.10 HSS Interface
    - Figure 13. UTOPIA Interface Example
    - 443.10.1 Signal Interface
      - Table 17. High-Speed, Serial Interface0
      - 45Table 18. High-Speed, Serial Interface 1
    - 3.10.2 Device Connection
      - SSP Interface
      - HSS Interface
  - 463.11 SSP Interface
    - Figure 14. H SS Interface Example
      - External Oscillato r
      - IntelIXP46X Product Line of Network Processors
    - 473.11.1 Signal Interface
    - 3.11.2 Device Connection
  - 483.12 PCI Interface
    - 3.12.1 Signal Interface
      - Table 20. PCI Controller (Sheet 1 of 2)
    - 493.12.2 PCI Interface Block Diagram
    - 503.12.3 Supporting 5 V PCI Interface
    - 513.12.4 PCI Option Interface
      - Figure 17. PCI 3.3 V to 5 V Logic Translation Interface
        32-Bit BUS
        3.3V LOGIC 5.0V LOGIC
        Intel
        IXP46X Product Line Network Processor
      - PCI Interface
      - PCI D evice_ 1 3.3V Logi c PCI D evice_2 3.3V Logi c PCI D evice_3 5.0V Logic PCI D evi ce_4
        Table 21. PCI Host/Option Interface Pin Description (Sheet 1 of 3)
        52Table 21. PCI Host/Option Interface Pin Description (Sheet 2 of 3)
    - 3.12.5 Design Notes
  - 533.13 JTAG Interface
    - 3.13.1 Signal Interface
  - 543.14 Input System Clock
    - 3.14.1 Clock Signals
    - 3.14.2 Clock Oscillator
    - 3.14.3 Device Connection
  - 553.15 Power
    - 563.15.1 De-Coupling Capacitance Recommendations
    - 3.15.2 VCC De-Coupling
    - 3.15.3 VCCP De-Coupling
    - 3.15.4 VCCM De-Coupling
    - 3.15.5 Power Sequence
    - 3.15.6 Reset Timing
- 594.0 General PCB Guide
  - 4.1 PCB Overview
  - 4.2 General Recommendations
  - 4.3 Component Selection
  - 4.4 Component Placement
  - 604.5 Stack-Up Selection
    - PCB
      - Inexpensive Manufactured by virtually all printed-circuit-board vendors
        Intel IXP45X and Intel IXP46X Product Line of Network ProcessorsCategory
        HDD February 2007 62 Document Number: 305261; Revsion: 004
        62Figure 20. 8 -Layer Stackup
        GND
        Figure 21. 6 -Layer Stackup
        POWER
        GND POWER
- 635.0 General Layout and Routing Guide
  - 5.1 Overview
  - 5.2 General Layout Guidelines
    - 5.2.1 General Component Spacing
  - 64VIAs
    - 66PGA or BGA Package
      - 5.2.2 Clock Signal Considerations
      - 675.2.3 SMII Signal Cons ide rations
      - 5.2.4 MII Signal Conside rations
      - 5.2.5 USB Cons iderations
      - 685.2.6 Cross-Talk
      - 5.2.7 EMI-Design C onsiderations
      - 695.2.8 Trace Impedance
      - 5.2.9 Power and Ground Plane
- 716.0 PCI Interface Design Considerations
  - 6.1 Electrical Interface
  - 6.2 Topology
  - 726.3 Clock Distribution
    - BBB
    - A
      - 736.3.1 Trace Le ngth Limits
        PCI D evi ces
        Clock Driver
      - 746.3.2 Routing Guidelines
      - 6.3.3 Signal Loading
- 757.0 DDR-SDRAM
  - 7.1 Introduction
    - 76DDR SDRAM
    - Intel
    - Product Line of Network Processors
      - February 2007 HDD Document Number: 305261, Revision: 004 79
      - DDR-SDRAMIntel IXP45X and Intel IXP46X Product Line of Network Processors
      - 79DDR 5
        Figure 29. Processor-DDR Interface: x16 Devices with ECC
      - VTTSignal Termination
      - DDR 1 DDR 2
      - DDR 3 DDR 4
        Intel
        IXP46X Product Line of Network Processors
      - DDR 6
        R
      - VTT Signal Terminati on
      - 7.1.1 Selecting VTT Power Supply
  - 80VTT
    - R
    - Vout
    - IXP46X DDR SDRAM
    - 817.1.2 Signal-Timing Analysis
      - Figure 31. DDR Command and Control Setup and Hold
      - Table 29. DDR Command and Control Setup and Hold Values
      - DDR_M_CLK Control/Command Valid
        Figure 32. DDR Data to DQS Read Timing Parameters
        82DQS
        Data
        D0 D1
        Table 30. DDR Data to DQS Read Timing Parameters
        Figure 33. DDR-Data-to-DQS-Write Timing Parameters
        Table 31. DDR Data to DQS Write Timing Parameters
        Figure 34. DDR-Clock-to-DQS-Write Timing Parameters
      - 83DQS Data Valid
      - Data
        DDR_M_CLK
        DQS
    - 847.1.3 Printed Circuit Board Layer Stackup
    - 857.1.4 Printed Circuit Board Controlled Impedance
    - 877.1.5 Timing Relationships
    - 887.1.6 Resistive Compensation Register (Rcomp)
    - 7.1.7 Routing Guidelines
      - 7.1.7.1 Clock Group
      - 897.1.7.2 Data, Command, and Control Groups
        Table 34. Clock Signal Group Routing Guidelines
        Table 35. Data, Command, and Control Group Routing Guidelines
    - 907.2 Simulation Results