| TTCAN | User’s Manual | Revision 1.6 | |||
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| CAN Base+0x48 | IF2 Arbitration 1 | 0x0000 | CAN appl. IF2 Register Set |
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| CAN Base+0x4A | IF2 Arbitration 2 | 0x0000 |
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| CAN Base+0x4C | IF2 Message Control | 0x0000 |
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| CAN Base+0x4E | IF2 Data A 1 | 0x0000 |
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| CAN Base+0x50 | IF2 Data A 2 | 0x0000 |
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| CAN Base+0x52 | IF2 Data B 1 | 0x0000 |
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| CAN Base+0x54 | IF2 Data B 2 | 0x0000 |
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| CAN Base+0x56 | 0x0000 | TTCAN config register |
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| CAN Base+0x58 | 0x1000 | TTCAN config register |
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| CAN Base+0x5A | 0x0000 | TTCAN status register |
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| CAN Base+0x5C | 0x0001 | TTCAN status register |
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| CAN Base+0x5E | — reserved | — 2) |
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| CAN Base+0x60 | Stop_Watch | 0x0000 | TTCAN status register |
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| CAN Base+0x62 | — reserved | — 2) |
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| CAN Base+0x64 | Global Time Preset | 0x0000 | TTCAN appl. register |
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| CAN Base+0x66 | Clock Control | 0x1000 | TTCAN appl. register |
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| CAN Base+0x68 | Sync_Mark | 0x0000 | TTCAN status register |
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| CAN Base+0x6A | — reserved | — 2) |
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| CAN Base+0x6C | Time Mark | 0x0000 | TTCAN appl. register |
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| CAN Base+0x6E | Gap Control | 0x0000 | TTCAN appl. register |
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| CAN | — reserved | — 2) |
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| CAN Base+0x80 | Transmission Request 1 | 0x0000 | CAN status register |
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| CAN Base+0x82 | Transmission Request 2 | 0x0000 | CAN status register |
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| CAN | — reserved | — 2) |
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| CAN Base+0x90 | New Data 1 | 0x0000 | CAN status register |
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| CAN Base+0x92 | New Data 2 | 0x0000 | CAN status register |
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| CAN | — reserved | — 2) |
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| CAN Base+0xA0 | Interrupt Pending 1 | 0x0000 | CAN status register |
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| CAN Base+0xA2 | Interrupt Pending 2 | 0x0000 | CAN status register |
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| CAN | — reserved | — 2) |
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| CAN Base+0xB0 | Message Valid 1 | 0x0000 | CAN status register |
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| CAN Base+0xB2 | Message Valid 2 | 0x0000 | CAN status register |
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about.fm |
| CAN | — reserved | — 2) |
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| 1) r signifies the actual value of the CAN_RX pin. |
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manual |
| 2) Reserved bits are read as ’0’ except for IFx Mask 2 Register where they are read as ’1’ |
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Figure 5: TTCAN Register Summary
3.1 Hardware Reset Description
After hardware reset, the registers of the TTCAN hold the values described in figure 5.
Additionally the Bus_Off state is reset and the output CAN_TX is set to recessive (HIGH). The value 0x0001 (Init = ‘1’) in the CAN Control Register enables the software initialisation. The TTCAN does not influence the CAN bus until the CPU resets Init to ‘0’.
The data in the Message RAM is (apart from the MsgVal, NewDat, TxRqst, and IntPnd bits) not affected by a hardware reset. After
BOSCH | - 16/77 - | 11.11.02 |
