Cpuifc, Ttcan | Bosch Appliances TTCAN guide

TTCAN

User’s Manual

Revision 1.6

2.2 Block Diagram

manual_about.fm

				CAN_TX
				CAN_Core
				CAN_RX
				CAN-Message
Clock
Reset				Message RAM
Control		1	2	Message RAM
		1	2	(single ported)
		Register	Register
	Interface
Address	Interface
Address
DataIN	Module	CPUIFC	CPUIFC
	Module	CPUIFC	CPUIFC	Message Handler
				Message Handler
DataOUT
Wait				Trigger Memory
				Trigger Memory
Interrupt				Trigger
				Trigger

SWT, EVT

TTCAN - Frame Synchronisation Entity

TMI

TTCAN

Figure 1: Block Diagram of the TTCAN

CAN_Core

CAN Protocol Controller and Rx/Tx Shift Register, handles all ISO 11898-1 protocol functions.

Message Handler

State Machine that controls the data transfer between the single ported Message RAM, the CAN_Core’s Rx/Tx Shift Register, and the CPU IFC Registers. It also handles acceptance ﬁltering and the interrupt setting as programmed in the Control and Conﬁguration Registers.

Message RAM / CPU IFC Registers

Single ported RAM, word-length = [CAN message & acceptance ﬁlter mask & control bits & status bits]. To ensure data consistency, all CPU accesses to the Message RAM are relayed through CPU IFC registers that have the same word-length as the Message RAM.

Frame Synchronisation Entity / Trigger Memory

State machine that controls the ISO 11898-4 time triggered communication. It synchronises itself to the reference messages on the CAN bus, controls Cycle Time and Global Time, and handles transmissions according to the predeﬁned message schedule, the system matrix. StopWatch Trigger, EVent Trigger, and Time Mark Interrupt are synchronisation interfaces. The Trigger Memory stores the time marks of the system matrix that are linked to the messages in the Message RAM.

Module Interface

Up to now the TTCAN module is provided with three different interfaces. An 8-bit interface for the Motorola HC08 controller a 16-bit interface to the TI TMS470 controller, and two 16-bit interfaces to the AMBA APB bus from ARM. They can easily be replaced by a user-deﬁned module interface.

BOSCH

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Bosch Appliances TTCAN user manual Cpuifc, Ttcan

Contents

Robert Bosch GmbH User’s Manual Copyright Notice and Proprietary Information Functional Overview 2.2. Block Diagram Operating Modes Change ControlConventions Scope References Terms and Abbreviations Can Application Ttcan Schedule Initialisation Ttcan ConfigurationTtcan Message Handling List of Figures Change History Change Control Current StatusConventions Helvetica bold Term Meaning Functional Overview Ttcan Cpuifc Can Message Transfer Operating Modes Software Initialisation Disabled Automatic Retransmission Test ModeTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back combined with Silent Mode Loop Back Mode Software control of Pin Cantx No Message RAM Mode Address Name Reset Value Ttcan Register Summary Hardware Reset Description DAR CCEEIE SIE Status Register addresses 0x03 No Error Error Counter addresses 0x05 Status InterruptsBit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C IFx Command Mask Registers Direction = WriteArb Direction = Read IFx Command Request RegistersControl ClrIntPnd Message Number BusyIFx Message Buffer Registers IFx Mask Registers IFx Message Control Registers IFx Data a and Data B RegistersMessage Object in the Message Memory Msk28-0 ID28-0Xtd Dir 26/77 11.11.02 Interrupt Register addresses 0x09 Message Handler Registers Transmission Request Registers New Data RegistersInterrupt Pending Registers 2 IF1 Data B1 and B2 Registers for Trigger Memory Access Message Valid 1 RegisterTrigger Number Type TT Operation Mode Register addresses 0x29TimeMark At CycleCount mod MPr2-0 Eecs RdlcTEW CCM TT Interrupt Enable Register addresses 0x31Bark AppWdL GTE CELGTW SWE RTO TT Error Level Register addresses 0x3F & 0x3E TT Cycle Count Register addresses 0x3D & 0x3CTUR Numerator Conﬁguration Low Register addresses 0x57 TUR Denominator Conﬁguration Register addresses 0x59 TUR Numerator Actual Registers addresses 0x5B & 0x5ATT StopWatch Register addresses 0x61 Qgtp QCSEcal Egtf DET TMCECS SWS TMG EPE 40/77 11.11.02 Data Transfer Between IFx Registers and Message RAM Internal can Message Handling Start Transmission of Messages in Event Driven can Communication Reception of Data Frame Acceptance Filtering of Received MessagesReception of Remote Frame Storing Received Messages in Fifo Buffers Conﬁguration of the Module Receive / Transmit Priority 1 Conﬁguration of the Bit Timing Sync PropSeg PhaseSeg1 PhaseSeg2Bit Time and Bit Rate Canclk input Nominal can Bit Time BRP Propagation Time Segment Phase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes 1.5 Conﬁguration of the can Protocol Controller Oscillator Tolerance Range Calculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate 2 Conﬁguration of the Message Memory Example for Bit Timing at low Baudrate 2.2 Conﬁguration of a Single Receive Object for Data Frames 2.1 Conﬁguration of a Transmit Object for Data Frames 2.3 Conﬁguration of a Fifo Buffer Handling of Interrupts Can Communication Updating a Transmit Object Reading Received Messages Changing a Transmit ObjectRequesting New Data for a Receive Object Reading from a Fifo Buffer CPU Handling of a Fifo Buffer Interrupt Driven Ttcan Timing Ttcan Conﬁguration TUR 510 125000 32.5 100/12 529/17Message Scheduling Trigger Memory 63/77 11.11.02 Message Objects Reference MessagePeriodic Transmit Message Event Driven Transmit Message Time SlavesPotential Time Masters Message Transmission Ttcan Message Handling Message ReceptionPeriodic Messages Event Driven Messages Stopwatch Ttcan Gap Control Cycle Time and Global Time Synchronisation Previous RefMark Ttcan Interrupt and Error Handling Conﬁguration Example Rdlc & TEW & CCM Register Remark Type & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Generic InterfaceCustomer Interface Canclk Canwaitb Timing of the Wait output signalBusy = ‘1’ Busy = ‘0’ Interrupt Timing EOF