Terms and Abbreviations, Term Meaning | Bosch Appliances TTCAN

TTCAN

User’s Manual

Revision 1.6

1.5 Terms and Abbreviations

This document uses the following terms and abbreviations.

Term	Meaning
CAN	Controller Area Network
BSP	Bit Stream Processor
BTL	Bit Timing Logic
CRC	Cyclic Redundancy Check Register
DLC	Data Length Code
EML	Error Management Logic
FSE	Frame Synchronisation Entity
FSM	Finite State Machine
NTU	Network Time Unit
TTCAN	Time Triggered CAN

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Bosch Appliances TTCAN user manual Terms and Abbreviations, Term Meaning

Contents

Robert Bosch GmbH User’s Manual Copyright Notice and Proprietary Information Change Control Functional Overview 2.2. Block Diagram Operating ModesConventions Scope References Terms and Abbreviations Can Application List of Figures Ttcan ConfigurationTtcan Schedule Initialisation Ttcan Message Handling Helvetica bold Change Control Current StatusChange History Conventions Term Meaning Functional Overview Ttcan Cpuifc Can Message Transfer Operating Modes Software Initialisation Test Mode Disabled Automatic RetransmissionTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back combined with Silent Mode Loop Back Mode Software control of Pin Cantx No Message RAM Mode Address Name Reset Value Ttcan Register Summary Hardware Reset Description SIE CCEDAR EIE Status Register addresses 0x03 No Error Status Interrupts Error Counter addresses 0x05Bit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C Direction = Write IFx Command Mask RegistersArb ClrIntPnd IFx Command Request RegistersDirection = Read Control IFx Mask Registers BusyMessage Number IFx Message Buffer Registers IFx Data a and Data B Registers IFx Message Control RegistersMessage Object in the Message Memory Dir ID28-0Msk28-0 Xtd 26/77 11.11.02 Interrupt Register addresses 0x09 Message Handler Registers New Data Registers Transmission Request RegistersInterrupt Pending Registers Message Valid 1 Register 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessTrigger Number MPr2-0 TT Operation Mode Register addresses 0x29Type TimeMark At CycleCount mod Rdlc EecsTEW AppWdL TT Interrupt Enable Register addresses 0x31CCM Bark SWE CELGTE GTW RTO TT Cycle Count Register addresses 0x3D & 0x3C TT Error Level Register addresses 0x3F & 0x3ETUR Numerator Conﬁguration Low Register addresses 0x57 TUR Numerator Actual Registers addresses 0x5B & 0x5A TUR Denominator Conﬁguration Register addresses 0x59TT StopWatch Register addresses 0x61 Egtf QCSQgtp Ecal SWS TMCDET ECS TMG EPE 40/77 11.11.02 Data Transfer Between IFx Registers and Message RAM Internal can Message Handling Start Transmission of Messages in Event Driven can Communication Storing Received Messages in Fifo Buffers Acceptance Filtering of Received MessagesReception of Data Frame Reception of Remote Frame Conﬁguration of the Module Receive / Transmit Priority Canclk input Nominal can Bit Time Sync PropSeg PhaseSeg1 PhaseSeg21 Conﬁguration of the Bit Timing Bit Time and Bit Rate BRP Propagation Time Segment Phase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes 1.5 Conﬁguration of the can Protocol Controller Oscillator Tolerance Range Calculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate 2 Conﬁguration of the Message Memory Example for Bit Timing at low Baudrate 2.2 Conﬁguration of a Single Receive Object for Data Frames 2.1 Conﬁguration of a Transmit Object for Data Frames 2.3 Conﬁguration of a Fifo Buffer Handling of Interrupts Can Communication Updating a Transmit Object Reading from a Fifo Buffer Changing a Transmit ObjectReading Received Messages Requesting New Data for a Receive Object CPU Handling of a Fifo Buffer Interrupt Driven Ttcan Timing Ttcan Conﬁguration 510 125000 32.5 100/12 529/17 TURMessage Scheduling Trigger Memory 63/77 11.11.02 Reference Message Message ObjectsPeriodic Transmit Message Time Slaves Event Driven Transmit MessagePotential Time Masters Event Driven Messages Ttcan Message Handling Message ReceptionMessage Transmission Periodic Messages Stopwatch Ttcan Gap Control Cycle Time and Global Time Synchronisation Previous RefMark Ttcan Interrupt and Error Handling Conﬁguration Example Rdlc & TEW & CCM Register Remark Type & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Interface GenericCustomer Interface Interrupt Timing Timing of the Wait output signalCanclk Canwaitb Busy = ‘1’ Busy = ‘0’ EOF