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TTCAN

User’s Manual

Revision 1.6

manual_about.fm

3.5.9 TT Global Time Register (addresses 0x35 & 0x34)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							Global_Time

				r								r

Global_Time Global Time of the TTCAN network 0x0000-0xFFFFActual Global Time value.

3.5.10 TT Cycle Time Register (addresses 0x37 & 0x36)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							Cycle_Time

				r								r

Cycle_Time Cycle Time of the TTCAN basic cycle 0x0000-0xFFFFActual Cycle Time value.

3.5.11 TT Local Time Register (addresses 0x39 & 0x38)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							Local_Time

				r								r

Local_Time Local Time of the TTCAN node 0x0000-0xFFFFActual Local Time value.

3.5.12 TT Master State Register (addresses 0x3B & 0x3A)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RTO

WfE

TMP2-0

SyncSt

MState

r

r

r

r

r

RTO

Ref_Trigger_Offset

0x00-0xFF

The actual value of the Ref_Trigger_Offset.

WfE

Wait for Event

one

The node waits for event triggered Reference Message.

zero

The node does not wait for event triggered Reference Message.

TMP2-0

Time Master Priority

0x0-0x7

The priority of the actual Time Master.

SyncSt

TTCAN Synchronisation State

0x0

Out of Synchronisation

0x1

Synchronising to TTCAN communication

0x2

In_Gap, Schedule suspended by Gap

0x3

In_Schedule, Synchronised to Schedule

MState

TTCAN Master State and Operating Mode

0x0

Node does not take part in TTCAN communication

0x1

Node is operating as Time Slave

0x2

Node is operating as Backup Time Master

0x3

Node is operating as Current Time Master

BOSCH

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11.11.02

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Bosch Appliances TTCAN user manual Rto

Contents

User’s Manual Robert Bosch GmbH Copyright Notice and Proprietary Information Change Control Functional Overview 2.2. Block Diagram Operating ModesConventions Scope References Terms and Abbreviations Can Application Ttcan Message Handling Ttcan ConfigurationTtcan Schedule Initialisation List of Figures Conventions Change Control Current StatusChange History Helvetica bold Term Meaning Functional Overview Cpuifc Ttcan Operating Modes Software Initialisation Can Message Transfer Test Mode Disabled Automatic RetransmissionTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back Mode Loop Back combined with Silent Mode No Message RAM Mode Software control of Pin Cantx Address Name Reset Value Hardware Reset Description Ttcan Register Summary EIE CCEDAR SIE No Error Status Register addresses 0x03 Status Interrupts Error Counter addresses 0x05Bit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C Direction = Write IFx Command Mask RegistersArb Control IFx Command Request RegistersDirection = Read ClrIntPnd IFx Message Buffer Registers BusyMessage Number IFx Mask Registers IFx Data a and Data B Registers IFx Message Control RegistersMessage Object in the Message Memory Xtd ID28-0Msk28-0 Dir 26/77 11.11.02 Message Handler Registers Interrupt Register addresses 0x09 New Data Registers Transmission Request RegistersInterrupt Pending Registers Message Valid 1 Register 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessTrigger Number TimeMark At CycleCount mod TT Operation Mode Register addresses 0x29Type MPr2-0 Rdlc EecsTEW Bark TT Interrupt Enable Register addresses 0x31CCM AppWdL GTW CELGTE SWE RTO TT Cycle Count Register addresses 0x3D & 0x3C TT Error Level Register addresses 0x3F & 0x3ETUR Numerator Conﬁguration Low Register addresses 0x57 TUR Numerator Actual Registers addresses 0x5B & 0x5A TUR Denominator Conﬁguration Register addresses 0x59TT StopWatch Register addresses 0x61 Ecal QCSQgtp Egtf ECS TMCDET SWS EPE TMG 40/77 11.11.02 Internal can Message Handling Data Transfer Between IFx Registers and Message RAM Transmission of Messages in Event Driven can Communication Start Reception of Remote Frame Acceptance Filtering of Received MessagesReception of Data Frame Storing Received Messages in Fifo Buffers Receive / Transmit Priority Conﬁguration of the Module Bit Time and Bit Rate Sync PropSeg PhaseSeg1 PhaseSeg21 Conﬁguration of the Bit Timing Canclk input Nominal can Bit Time Propagation Time Segment BRP Phase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes Oscillator Tolerance Range 1.5 Conﬁguration of the can Protocol Controller Calculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate Example for Bit Timing at low Baudrate 2 Conﬁguration of the Message Memory 2.1 Conﬁguration of a Transmit Object for Data Frames 2.2 Conﬁguration of a Single Receive Object for Data Frames 2.3 Conﬁguration of a Fifo Buffer Can Communication Handling of Interrupts Updating a Transmit Object Requesting New Data for a Receive Object Changing a Transmit ObjectReading Received Messages Reading from a Fifo Buffer CPU Handling of a Fifo Buffer Interrupt Driven Ttcan Conﬁguration Ttcan Timing 510 125000 32.5 100/12 529/17 TURMessage Scheduling Trigger Memory 63/77 11.11.02 Reference Message Message ObjectsPeriodic Transmit Message Time Slaves Event Driven Transmit MessagePotential Time Masters Periodic Messages Ttcan Message Handling Message ReceptionMessage Transmission Event Driven Messages Ttcan Gap Control Stopwatch Cycle Time and Global Time Synchronisation Ttcan Interrupt and Error Handling Previous RefMark Conﬁguration Example Register Remark Rdlc & TEW & CCM Type & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Interface GenericCustomer Interface Busy = ‘1’ Busy = ‘0’ Timing of the Wait output signalCanclk Canwaitb Interrupt Timing EOF