Qcs, Qgtp, Ecal, Egtf, Elt | Bosch Appliances TTCAN specification

TTCAN

User’s Manual

Revision 1.6

manual_about.fm

3.5.19 TT Global Time Preset Register (addresses 0x65 & 0x64)

15		14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								GTDiff

				rw									rw
GTDiff		Global Time Preset
		0x0000-0x7FFFMaster_Ref_Mark = Master_Ref_Mark + GTDiff.
		0x8000			reserved.
		0x8001-0xFFFF Master_Ref_Mark = Master_Ref_Mark - (0x10000-GTDiff).

The Global Time Preset takes effect when the node is the current Time Master and when ‘1’ is written to SGT in the TT Clock Control register. The next Reference Message will be transmitted with the modiﬁed Master_Ref_Mark and with Disc_Bit = ‘1’, presetting the Global Time in all nodes simultaneously.

GTDiff is reset to 0x0000 each time a Reference Message with Disc_Bit = ‘1’ becomes valid or if the node is not the current time master.

GTDiff is locked (and WGTD is ‘1’) after setting SGT until the Reference Message with Disc_Bit = ‘1’ becomes valid or until the node is no longer the current time master.

3.5.20 TT Clock Control Register (addresses 0x67 & 0x66)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

ldSDL

QCS

QGTP

ECAL

EGTF

ELT

TMC

DET

ECS

SWS

WGTD

SGT

rw

r

r

rw

rw

rw

rw

rw

rw

rw

r

rw

ldSDL

ld(Synchronisation Deviation Limit)

0x0-0x7

Synchronisation Deviation ≤ 2(ldSDL + 5).

QCS

Quality of Clock Speed

one

SD ≤ SDL (always true in TTCAN Level 1).

zero

Local clock speed not synchronised to Time Master clock speed.

QGTP

Quality of Global Time Phase

one

Global Time in phase with Time Master.

zero

Global Time not valid (always true in TTCAN Level 1).

ECAL

Enable Clock Calibration

one

The automatic clock calibration in TTCAN Level2 is enabled.

zero

The automatic clock calibration in TTCAN Level2 is disabled.

EGTF

Enable Global Time Filtering

one

The Global Time ﬁltering in TTCAN Level2 is enabled.

zero

The Global Time ﬁltering in TTCAN Level2 is disabled.

ELT

Enable Local Time

one

The Local Time is enabled.

zero

The Local Time is stopped (default after hardware reset).

Note : ELT can only be written during Conﬁguration Mode. It may not be set before the TUR conﬁgura- tion registers are programmed. Once the Local Time is started, is remains active until the CPU writes ELT to ‘0’ or until the next hardware reset. Local Time is also started by resetting Init in the CAN Control register.

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11.11.02

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Bosch Appliances TTCAN user manual Qcs, Qgtp, Ecal, Egtf, Elt

Contents

Robert Bosch GmbH User’s Manual Copyright Notice and Proprietary Information Change Control Functional Overview 2.2. Block Diagram Operating ModesConventions Scope References Terms and Abbreviations Can Application Ttcan Schedule Initialisation Ttcan ConfigurationTtcan Message Handling List of Figures Change History Change Control Current StatusConventions Helvetica bold Term Meaning Functional Overview Ttcan Cpuifc Can Message Transfer Operating Modes Software Initialisation Test Mode Disabled Automatic RetransmissionTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back combined with Silent Mode Loop Back Mode Software control of Pin Cantx No Message RAM Mode Address Name Reset Value Ttcan Register Summary Hardware Reset Description DAR CCEEIE SIE Status Register addresses 0x03 No Error Status Interrupts Error Counter addresses 0x05Bit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C Direction = Write IFx Command Mask RegistersArb Direction = Read IFx Command Request RegistersControl ClrIntPnd Message Number BusyIFx Message Buffer Registers IFx Mask Registers IFx Data a and Data B Registers IFx Message Control RegistersMessage Object in the Message Memory Msk28-0 ID28-0Xtd Dir 26/77 11.11.02 Interrupt Register addresses 0x09 Message Handler Registers New Data Registers Transmission Request RegistersInterrupt Pending Registers Message Valid 1 Register 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessTrigger Number Type TT Operation Mode Register addresses 0x29TimeMark At CycleCount mod MPr2-0 Rdlc EecsTEW CCM TT Interrupt Enable Register addresses 0x31Bark AppWdL GTE CELGTW SWE RTO TT Cycle Count Register addresses 0x3D & 0x3C TT Error Level Register addresses 0x3F & 0x3ETUR Numerator Conﬁguration Low Register addresses 0x57 TUR Numerator Actual Registers addresses 0x5B & 0x5A TUR Denominator Conﬁguration Register addresses 0x59TT StopWatch Register addresses 0x61 Qgtp QCSEcal Egtf DET TMCECS SWS TMG EPE 40/77 11.11.02 Data Transfer Between IFx Registers and Message RAM Internal can Message Handling Start Transmission of Messages in Event Driven can Communication Reception of Data Frame Acceptance Filtering of Received MessagesReception of Remote Frame Storing Received Messages in Fifo Buffers Conﬁguration of the Module Receive / Transmit Priority 1 Conﬁguration of the Bit Timing Sync PropSeg PhaseSeg1 PhaseSeg2Bit Time and Bit Rate Canclk input Nominal can Bit Time BRP Propagation Time Segment Phase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes 1.5 Conﬁguration of the can Protocol Controller Oscillator Tolerance Range Calculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate 2 Conﬁguration of the Message Memory Example for Bit Timing at low Baudrate 2.2 Conﬁguration of a Single Receive Object for Data Frames 2.1 Conﬁguration of a Transmit Object for Data Frames 2.3 Conﬁguration of a Fifo Buffer Handling of Interrupts Can Communication Updating a Transmit Object Reading Received Messages Changing a Transmit ObjectRequesting New Data for a Receive Object Reading from a Fifo Buffer CPU Handling of a Fifo Buffer Interrupt Driven Ttcan Timing Ttcan Conﬁguration 510 125000 32.5 100/12 529/17 TURMessage Scheduling Trigger Memory 63/77 11.11.02 Reference Message Message ObjectsPeriodic Transmit Message Time Slaves Event Driven Transmit MessagePotential Time Masters Message Transmission Ttcan Message Handling Message ReceptionPeriodic Messages Event Driven Messages Stopwatch Ttcan Gap Control Cycle Time and Global Time Synchronisation Previous RefMark Ttcan Interrupt and Error Handling Conﬁguration Example Rdlc & TEW & CCM Register Remark Type & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Interface GenericCustomer Interface Canclk Canwaitb Timing of the Wait output signalBusy = ‘1’ Busy = ‘0’ Interrupt Timing EOF