TTCAN | User’s Manual | Revision 1.6 |
manual_about.fm
3.2 CAN Protocol Related Registers
These registers are related to the CAN protocol controller in the CAN Core. They control the operating modes and the configuration of the CAN bit timing and provide status information.
3.2.1 CAN Control Register (addresses 0x01 & 0x00)
15 | 14 | 13 | 12 |
| 11 |
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| 8 | 7 | 6 | 5 | 4 |
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| 1 | 0 | |
| res | res | res | res |
| res |
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| res | Test | CCE | DAR | res |
| EIE |
| SIE |
| IE | Init |
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| r | r | r | r | r | r | r | r | rw | rw | rw | r | rw | rw | rw | rw | |||||||
Test |
| Test Mode Enable |
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| one | Test Mode. |
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| zero | Normal Operation. |
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CCE |
| Configuration Change Enable |
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| one | The CPU has write access to the configuration registers (while Init = one). | |||||||||||||||||||
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| zero | The CPU has no write access to the configuration registers. |
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DAR |
| Disable Automatic Retransmission |
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| one | Automatic Retransmission disabled. |
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| zero | Automatic Retransmission of not successful messages enabled. |
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EIE |
| Error Interrupt Enable |
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| one | Enabled - A change in the bits BOff or EWarn in the Status Register will | |||||||||||||||||||
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| zero | Disabled - No Error Status Interrupt will be generated. |
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SIE |
| Status Change Interrupt Enable |
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| one | Enabled - An interrupt will be generated when a message transfer is suc- | |||||||||||||||||||
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| cessfully completed or a CAN bus error is detected. |
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| zero | Disabled - No Status Change Interrupt will be generated. |
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IE |
| Module Interrupt Enable |
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| one | Enabled - Interrupts will set IRQ_B to LOW. IRQ_B remains LOW until all | |||||||||||||||||||
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| pending interrupts are processed. |
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| zero | Disabled - Module Interrupt IRQ_B is always HIGH. |
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Init |
| Initialization |
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| one | Initialization is started. |
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| zero | Normal Operation. |
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The configuration registers controlled by CCE are the Bit Timing Register, the BRP Extension Register, and the TT Operation Mode Register.
Note : The Bus_Off recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by set- ting or resetting Init. If the device goes Bus_Off, it will set Init of its own accord, stopping all bus activities. Once Init has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operations. At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset.
During the waiting time after the resetting of Init, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to the Status Register, enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the proceeding of the Bus_Off recovery sequence.
BOSCH | - 17/77 - | 11.11.02 |
