TTCAN | User’s Manual | Revision 1.6 |
manual_about.fm
Received messages with identifiers matching to a FIFO Buffer are stored into a Message Object of this FIFO Buffer, starting with the Message Object with the lowest message number.
When a message is stored into a Message Object of a FIFO Buffer the NewDat bit of this Message Object is set. By setting NewDat while EoB is ‘0’ the Message Object is locked for further write accesses by the Message Handler until the CPU has cleared the NewDat bit.
Messages are stored into a FIFO Buffer until the last Message Object of this FIFO Buffer is reached. If none of the preceding Message Objects is released by writing NewDat to ‘0’, all further messages for this FIFO Buffer will be written into the last Message Object of the FIFO Buffer (EoB = ‘1’) and therefore overwrite previous messages.
4.1.5 Receive / Transmit Priority
The receive/transmit priority for the Message Objects is attached to the message number, not to the CAN identifier. Message Object 1 has the highest priority, while Message Object 32 has the lowest priority. If more than one transmission request is pending, they are serviced due to the priority of the corresponding Message Object, so the messages with the highest priority should be placed in the Message Objects with the lowest numbers.
4.2 Configuration of the Module
After the hardware reset, the Init bit in the CAN Control Register is set and all CAN protocol functions are disabled. The configuration of the module (bit timing and Message Objects) has to be completed before the CAN protocol functions are enabled.
The configuration of the bit timing requires that the CCE bit in the CAN Control Register is set additionally to Init. This is not required for the configuration of the Message Objects.
The configuration of the TTCAN functions (see chapter 5) requires that TTMode is set to “Configuration Mode”.
The bits MsgVal, NewDat, IntPnd, and TxRqst of the Message Objects are reset to ‘0’ by the hardware reset, the other contents of the Message RAM are not affected by a hardware reset. The configuration of a Message Object is done by programming Mask, Arbitration, Control and Data field of one of the two interface register sets to the desired values. By writing to the corresponding IFx Command Request Register, the IFx Message Buffer Registers are loaded into the addressed Message Object in the Message RAM.
All the Message Objects must be initialized by the CPU or they must be not valid, and the bit timing must be configured before the CPU clears the Init bit in the CAN Control Register.
The CPU may enable the interrupt line (setting IE to ‘1’) at the same time when it clears Init and CCE. The status interrupts EIE and SIE may be enabled simultaneously. If EIE is enabled, a status interrupt will be generated each time one of the error counters reaches or leaves the error warning level of 96 of when the Bus_Off state changes. If SIE is enabled, an interrupt will be generated each time when a message transfer is successfully completed or a CAN bus error is detected. The Last Error Code LEC in the Status Register allows the interrupt service routine to analyse the CAN bus errors.
When the Init bit in the CAN Control Register is cleared, the CAN Protocol Controller state machine of the CAN_Core and the Message Handler State Machine control the TTCAN’s internal data flow. Received messages that pass the acceptance filtering are stored into the Message RAM, messages with pending transmission request are loaded into the CAN_Core’s Shift Register and are transmitted via the CAN bus.
BOSCH | - 44/77 - | 11.11.02 |
