TTCAN | User’s Manual | Revision 1.6 |
manual_about.fm
operates according to ISO
ETT in the Matrix Limits registers specifies the number of Expected Tx_Triggers in the System Matrix. This is the sum of the Tx_Triggers for Exclusive, single Arbitrating and Merged Arbitrating Windows, excluding the Tx_Ref_Triggers. Note that this is usually not the number of Tx_Triggers in the Trigger Memory; the number of Basic Cycles in the System Matrix and the Trigger’s Repeat Factors have to be taken into account. An inaccurate configuration of ETT will result in either a Tx_Underflow (Error level 1) or in a Tx_Overflow (Error level 2).
CCM specifies the number of the last Basic Cycle in the System Matrix. The counting of Basic Cycles starts at 0, so in a System Matrix consisting of 8 Basic Cycles CCM would be 7. CCM is ignored by Time Slaves, a receiver of a Reference Message considers the received Cycle_Count as the valid Cycle_Count for the actual Basic Cycle.
RDLC specifies the Data Length Code of the Reference Messages transmitted by a potential Time Master. It has to be at least 0x1 for TTCAN Level 1 and 0x4 for TTCAN Level 2.
TEW specifies the length of the Tx_Enable Window in NTUs. The Tx_Enable Window is that period of time at the beginning of a Time Window where a transmission may be started. If a transmission of a message cannot be started inside the Tx_Enable Window, because of e.g. a slight overlap from the previous Time Window’s message, the transmission cannot be started in that Time Window at all. TEW has to be chosen with respect to the network’s synchronisation quality and with respect to the relation between the length of the Time Windows and the length of the messages.
Which interrupt sources to enable in the TT Interrupt Enable register is application specific. Write accesses to the Interrupt Enable register are not restricted to the Configuration Mode.
5.1.3 Trigger Memory
The Trigger Memory holds place for up to 32 Triggers. The Trigger information consists of Time_Mark, Message Number, Cycle_Code, and Trigger Type.
The Time_Mark defines at which Cycle Time a the Trigger becomes active.
Message Number and Cycle_Code are defined for all Triggers, but they are ignored for the Trigger Types Tx_Ref_Trigger, Tx_Ref_Trigger_Gap, Watch_Trigger, Watch_Trigger_Gap, and EndOfList. The Reference Message is linked to Message Object Number 1 by hardware and neither the Watch_Triggers nor the EndOfList Trigger are linked to any Message Object.
Eight different Trigger Types are available :
Tx_Ref_Trigger and Tx_Ref_Trigger_Gap cause the transmission of a Reference Message by a Time Master. A Configuration Error (Error level 3) is detected when a Time Slave encounters a Tx_Ref_Trigger(_Gap) in its Trigger Memory. Tx_Ref_Trigger_Gap is only used for the Event Synchronised Time Triggered Operation mode. In that mode, Tx_Ref_Trigger is ignored when the TTCAN Synchronisation State SyncSt is In_Gap.
Watch_Trigger and Watch_Trigger_Gap check for missing Reference Messages. They are used by both Time Masters and Time Slaves. Watch_Trigger_Gap is only used for the Event Synchronised Time Triggered Operation mode. In that mode, Watch_Trigger is ignored when the TTCAN Synchronisation State SyncSt is In_Gap.
Tx_Trigger_Single and Tx_Trigger_Merged both cause the start of a transmission, they define the start of Time Windows. Tx_Trigger_Single may be used for Exclusive Time Windows and
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