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TTCAN

User’s Manual

Revision 1.6

When the CPU initiates a data transfer between the IFx Registers and Message RAM, the Message Handler sets the Busy bit in the respective Command Request Register to ‘1’. After the transfer has completed, the Busy bit is set back to ‘0’ (see ﬁgure 8). If the optional wait- function is implemented in the module’s CPU interface, the CPU is halted while the Busy bit is set to ‘1’, see chapter 6.2.

START

No

Write Command Request Register

					Yes
					Yes

				Busy = 1

	No							Yes
	No			WR/RD = 1				Yes




						Read Message Object to IFx
						Read Message Object to IFx


Read Message Object to IFx
Read Message Object to IFx

							Write IFx to Message RAM

Busy = 0

manual_about.fm

Figure 8: Data Transfer between IFx Registers and Message RAM

4.1.2 Transmission of Messages in Event Driven CAN Communication

If the shift register of the CAN_Core cell is ready for loading and if there is no data transfer between the IFx Registers and Message RAM, the MsgVal bits in the Message Valid Register TxRqst bits in the Transmission Request Register are evaluated. The valid Message Object with the highest priority pending transmission request is loaded into the shift register by the Message Handler and the transmission is started. The Message Object’s NewDat bit is reset.

After a successful transmission and if no new data was written to the Message Object (NewDat = ‘0’) since the start of the transmission, the TxRqst bit will be reset. If TxIE is set, IntPnd will be set after a successful transmission. If the TTCAN has lost the arbitration or if an error occurred during the transmission, the message will be retransmitted as soon as the CAN bus is free again. If meanwhile the transmission of a message with higher priority has been requested, the messages will be transmitted in the order of their priority.

If DAR is set (Disable Automatic Retransmission), TxRqst will be reset when the message is loaded into the CAN_Core, NewDat will be reset after the successful transmission.

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11.11.02

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Bosch Appliances TTCAN user manual Transmission of Messages in Event Driven can Communication, Start

Contents

User’s Manual Robert Bosch GmbH Copyright Notice and Proprietary Information Functional Overview 2.2. Block Diagram Operating Modes Change ControlConventions Scope References Terms and Abbreviations Can Application Ttcan Message Handling Ttcan ConfigurationTtcan Schedule Initialisation List of Figures Conventions Change Control Current StatusChange History Helvetica bold Term Meaning Functional Overview Cpuifc Ttcan Operating Modes Software Initialisation Can Message Transfer Disabled Automatic Retransmission Test ModeTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back Mode Loop Back combined with Silent Mode No Message RAM Mode Software control of Pin Cantx Address Name Reset Value Hardware Reset Description Ttcan Register Summary EIE CCEDAR SIE No Error Status Register addresses 0x03 Error Counter addresses 0x05 Status InterruptsBit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C IFx Command Mask Registers Direction = WriteArb Control IFx Command Request RegistersDirection = Read ClrIntPnd IFx Message Buffer Registers BusyMessage Number IFx Mask Registers IFx Message Control Registers IFx Data a and Data B RegistersMessage Object in the Message Memory Xtd ID28-0Msk28-0 Dir 26/77 11.11.02 Message Handler Registers Interrupt Register addresses 0x09 Transmission Request Registers New Data RegistersInterrupt Pending Registers 2 IF1 Data B1 and B2 Registers for Trigger Memory Access Message Valid 1 RegisterTrigger Number TimeMark At CycleCount mod TT Operation Mode Register addresses 0x29Type MPr2-0 Eecs RdlcTEW Bark TT Interrupt Enable Register addresses 0x31CCM AppWdL GTW CELGTE SWE RTO TT Error Level Register addresses 0x3F & 0x3E TT Cycle Count Register addresses 0x3D & 0x3CTUR Numerator Conﬁguration Low Register addresses 0x57 TUR Denominator Conﬁguration Register addresses 0x59 TUR Numerator Actual Registers addresses 0x5B & 0x5ATT StopWatch Register addresses 0x61 Ecal QCSQgtp Egtf ECS TMCDET SWS EPE TMG 40/77 11.11.02 Internal can Message Handling Data Transfer Between IFx Registers and Message RAM Transmission of Messages in Event Driven can Communication Start Reception of Remote Frame Acceptance Filtering of Received MessagesReception of Data Frame Storing Received Messages in Fifo Buffers Receive / Transmit Priority Conﬁguration of the Module Bit Time and Bit Rate Sync PropSeg PhaseSeg1 PhaseSeg21 Conﬁguration of the Bit Timing Canclk input Nominal can Bit Time Propagation Time Segment BRP Phase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes Oscillator Tolerance Range 1.5 Conﬁguration of the can Protocol Controller Calculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate Example for Bit Timing at low Baudrate 2 Conﬁguration of the Message Memory 2.1 Conﬁguration of a Transmit Object for Data Frames 2.2 Conﬁguration of a Single Receive Object for Data Frames 2.3 Conﬁguration of a Fifo Buffer Can Communication Handling of Interrupts Updating a Transmit Object Requesting New Data for a Receive Object Changing a Transmit ObjectReading Received Messages Reading from a Fifo Buffer CPU Handling of a Fifo Buffer Interrupt Driven Ttcan Conﬁguration Ttcan Timing TUR 510 125000 32.5 100/12 529/17Message Scheduling Trigger Memory 63/77 11.11.02 Message Objects Reference MessagePeriodic Transmit Message Event Driven Transmit Message Time SlavesPotential Time Masters Periodic Messages Ttcan Message Handling Message ReceptionMessage Transmission Event Driven Messages Ttcan Gap Control Stopwatch Cycle Time and Global Time Synchronisation Ttcan Interrupt and Error Handling Previous RefMark Conﬁguration Example Register Remark Rdlc & TEW & CCM Type & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Generic InterfaceCustomer Interface Busy = ‘1’ Busy = ‘0’ Timing of the Wait output signalCanclk Canwaitb Interrupt Timing EOF