TTCAN | User’s Manual | Revision 1.6 |
manual_about.fm
‘0’), it is programmed to ID28 - ID18, ID17 - ID0 can then be disregarded. When a Remote Frame with an
The Data Length Code
If the RxIE bit is set, the IntPnd bit will be set when a received Remote Frame is accepted and stored in the Message Object.
4.3 CAN Communication
When the initialisation is finished, the TTCAN module synchronises itself to the traffic on the CAN bus. It does an acceptance filtering on received messages and stored those frames that are accepted into the designated Message Objects. The application program has to update the data of the messages to be transmitted and has to enable and request their transmission. The transmission is requested automatically when a matching Remote Frame is received or in time triggered communication.
The application program reads messages that are received and accepted. Messages that are not read before the next messages is accepted for the same Message Object will be overwritten. The Message Objects of a FIFO buffer need to be read and cleared before the next batch of messages can be stored. Depending on the configuration, the messages may be read
If one of the Interface Register sets is used only for reading of received messages its Command Mask Register may be kept constant at 0x7F, meaning that always the whole Message Object is transferred into the Interface Register set; NewDat and IntPnd are reset.
To update the data bytes of a message to be transmitted, the Command Mask Register should be set to 0x87 (all transmit messages in C_CAN emulation mode or event triggered message in arbitrating time window) or to 0x83 (time triggered message in exclusive time window).
Note : After the update of the Transmit Object, the Interface Register set will contain a copy of the actual contents of the object, including the part that had not been updated.
4.3.1 Handling of Interrupts
The TTCAN module provides several interrupt sources which share a common interrupt line. The common interrupt line to the CPU can be enabled/disabled by IE. The module’s interrupt sources can be enabled/disabled separately, by the TT Interrupt Enable Register, by the CAN Control Register bits SIE and EIE, or by the RxIE and TxIE bits of each Message Object. The source of a pending interrupt is shown by the CAN Interrupt Register.
The Status Interrupt and the TTCAN Interrupt have the highest priority. Among the message interrupts, the Message Object’ s interrupt priority decreases with increasing Message Number.
If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order. An interrupt remains pending until the CPU has cleared it.
A message interrupt is cleared by clearing the Message Object’s IntPnd bit. The Status Interrupt is cleared by reading the Status Register. The TTCAN Interrupt is cleared by reading the TT Interrupt Vector Register.
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