Type, TimeMark At CycleCount mod, MPr2-0 | Bosch Appliances TTCAN

TTCAN

User’s Manual

Revision 1.6

In the Trigger Memory, the Triggers must be sorted according to their Time_Marks. There may not be two Triggers that are active at the same Cycle Time and Cycle_Count. For details see chapter 5.1.3.

Type	Trigger Type
	0	Tx_Ref_Trigger	valid when not in Gap
	1	Tx_Ref_Trigger_Gap	valid when in Gap
	2	Tx_Trigger_Single	Start a transmission
	3	Tx_Trigger_Merged	Start a Merged Arbitrating Window
	4	Watch_Trigger	valid when not in Gap
	5	Watch_Trigger_Gap	valid when in Gap
	6	Rx_Trigger	Check for reception
	7	EndOfList	illegal type, causes conﬁg-error

Message Number
0x00	Trigger is valid for Message 32
0x01-0x1F	Trigger is valid for Message 1 to Message 31

Cycle_Code Cycle_Count for which the Trigger is valid 0b000000x valid for all Cycles 0b000001c valid every second Cycle 0b00001cc valid every fourth Cycle 0b0001ccc valid every eighth Cycle 0b001cccc valid every sixteenth Cycle 0b01ccccc valid every thirty-second Cycle 0b1cccccc valid every sixty-fourth Cycle

Time_Mark

at (Cycle_Count mod 2)	= c
at (Cycle_Count mod 4)	= cc
at (Cycle_Count mod 8)	= ccc
at (Cycle_Count mod 16)	= cccc
at (Cycle_Count mod 32)	= ccccc
at (Cycle_Count mod 64)	= cccccc

manual_about.fm

0x0000-0xFFFFCycle Time for which the trigger becomes active.

Note : The Message Number must be “1” for Type Tx_Ref_Trigger and Tx_Ref_Trigger_Gap. The Message Number is not regarded for Type Watch_Trigger, Watch_Trigger_Gap, and EndOf- List. The Time_Mark is not regarded for Trigger Type EndOfList. The Cycle_Count is only regarded for Type Rx_Trigger, Tx_Trigger_Single, and Tx_Trigger_Merged.

3.5.3 TT Operation Mode Register (addresses 0x29 & 0x28)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
res			Init_Ref_Offset					TM		MPR2-0		L2	EECS	TTMode

r				rw				rw		rw		rw	rw		rw

Init_Ref_Offset Initial Reference Trigger Offset

0x00-0x7Fpositive offset (Initial offset may not be negative).

TM	Time Master
	one	The node is a (potential) Time Master.
	zero	The node will never be a Time Master.
MPr2-0	Time Master Priority (last three bits of Reference Message’s identiﬁer)
	0x0-0x7	The priority of this node (0 is highest priority).
L2	Level 2
	one	The node operates in TTCAN Level 2.
	zero	The node operates in TTCAN Level 1.

BOSCH

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11.11.02

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Bosch Appliances TTCAN user manual Type, TimeMark At CycleCount mod, TT Operation Mode Register addresses 0x29, MPr2-0

Contents

User’s Manual Robert Bosch GmbH Copyright Notice and Proprietary Information Functional Overview 2.2. Block Diagram Operating Modes Change ControlConventions Scope References Terms and Abbreviations Can Application Ttcan Message Handling Ttcan ConfigurationTtcan Schedule Initialisation List of Figures Conventions Change Control Current StatusChange History Helvetica bold Term Meaning Functional Overview Cpuifc Ttcan Operating Modes Software Initialisation Can Message Transfer Disabled Automatic Retransmission Test ModeTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back Mode Loop Back combined with Silent Mode No Message RAM Mode Software control of Pin Cantx Address Name Reset Value Hardware Reset Description Ttcan Register Summary EIE CCEDAR SIE No Error Status Register addresses 0x03 Error Counter addresses 0x05 Status InterruptsBit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C IFx Command Mask Registers Direction = WriteArb Control IFx Command Request RegistersDirection = Read ClrIntPnd IFx Message Buffer Registers BusyMessage Number IFx Mask Registers IFx Message Control Registers IFx Data a and Data B RegistersMessage Object in the Message Memory Xtd ID28-0Msk28-0 Dir 26/77 11.11.02 Message Handler Registers Interrupt Register addresses 0x09 Transmission Request Registers New Data RegistersInterrupt Pending Registers 2 IF1 Data B1 and B2 Registers for Trigger Memory Access Message Valid 1 RegisterTrigger Number TimeMark At CycleCount mod TT Operation Mode Register addresses 0x29Type MPr2-0 Eecs RdlcTEW Bark TT Interrupt Enable Register addresses 0x31CCM AppWdL GTW CELGTE SWE RTO TT Error Level Register addresses 0x3F & 0x3E TT Cycle Count Register addresses 0x3D & 0x3CTUR Numerator Conﬁguration Low Register addresses 0x57 TUR Denominator Conﬁguration Register addresses 0x59 TUR Numerator Actual Registers addresses 0x5B & 0x5ATT StopWatch Register addresses 0x61 Ecal QCSQgtp Egtf ECS TMCDET SWS EPE TMG 40/77 11.11.02 Internal can Message Handling Data Transfer Between IFx Registers and Message RAM Transmission of Messages in Event Driven can Communication Start Reception of Remote Frame Acceptance Filtering of Received MessagesReception of Data Frame Storing Received Messages in Fifo Buffers Receive / Transmit Priority Conﬁguration of the Module Bit Time and Bit Rate Sync PropSeg PhaseSeg1 PhaseSeg21 Conﬁguration of the Bit Timing Canclk input Nominal can Bit Time Propagation Time Segment BRP Phase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes Oscillator Tolerance Range 1.5 Conﬁguration of the can Protocol Controller Calculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate Example for Bit Timing at low Baudrate 2 Conﬁguration of the Message Memory 2.1 Conﬁguration of a Transmit Object for Data Frames 2.2 Conﬁguration of a Single Receive Object for Data Frames 2.3 Conﬁguration of a Fifo Buffer Can Communication Handling of Interrupts Updating a Transmit Object Requesting New Data for a Receive Object Changing a Transmit ObjectReading Received Messages Reading from a Fifo Buffer CPU Handling of a Fifo Buffer Interrupt Driven Ttcan Conﬁguration Ttcan Timing TUR 510 125000 32.5 100/12 529/17Message Scheduling Trigger Memory 63/77 11.11.02 Message Objects Reference MessagePeriodic Transmit Message Event Driven Transmit Message Time SlavesPotential Time Masters Periodic Messages Ttcan Message Handling Message ReceptionMessage Transmission Event Driven Messages Ttcan Gap Control Stopwatch Cycle Time and Global Time Synchronisation Ttcan Interrupt and Error Handling Previous RefMark Conﬁguration Example Register Remark Rdlc & TEW & CCM Type & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Generic InterfaceCustomer Interface Busy = ‘1’ Busy = ‘0’ Timing of the Wait output signalCanclk Canwaitb Interrupt Timing EOF