TTCAN | User’s Manual | Revision 1.6 |
manual_about.fm
The interrupt identifier IntId in the Interrupt Register indicates the cause of the interrupt. When no interrupt is pending, the register will hold the value zero. If the value of the Interrupt Register is different from zero, then there is an interrupt pending and, if IE is set, the interrupt line to the CPU is active. The interrupt line remains active until the Interrupt Register is back to value zero (the cause of the interrupt is reset) or until IE is reset.
The value 0x4000 or 0xC000 indicates that an interrupt is pending in the TT Interrupt Vector Register and is enabled in the TT Interrupt Enable Register.
The value 0x8000 or 0xC000 indicates that an interrupt is pending because the CAN Core has updated (not necessarily changed) the Status Register (Error Interrupt or Status Interrupt). This interrupt has the highest priority. The CPU can update (reset) the status bits RxOk, TxOk and LEC, but a write access of the CPU to the Status Register can never generate or reset an interrupt.
All other values indicate that the source of the interrupt is one of the Message Objects, IntId points to the pending message interrupt with the highest interrupt priority.
The CPU controls whether a change of the Status Register may cause an interrupt (bits EIE and SIE in the CAN Control Register) and whether the interrupt line becomes active when the Interrupt Register is different from zero (bit IE in the CAN Control Register). The Interrupt Register will be updated even when IE is reset.
The Last Error Code LEC in the Status Register allows the interrupt service routine to analyse the CAN bus errors. AckError e.g. indicates that no other node is active on the CAN bus.
The CPU has two possibilities to follow the source of a message interrupt. First it can follow the IntId in the Interrupt Register and second it can poll the Interrupt Pending Register (see section 3.4.4).
An interrupt service routine reading the message that is the source of the interrupt may read the message and reset the Message Object’s IntPnd at the same time (bit ClrIntPnd in the Command Mask Register). When IntPnd is cleared, the Interrupt Register will point to the next Message Object with a pending interrupt.
4.3.2 Updating a Transmit Object
The CPU may update the data bytes of a Transmit Object any time via the IFx Interface Registers, neither MsgVal nor TxRqst have to be reset before the update.
Even if only a part of the data bytes are to be updated, all four bytes of the corresponding IFx Data A Register or IFx Data B Register have to be valid before the content of that register is transferred to the Message Object. Either the CPU has to write all four bytes into the IFx Data Register or the Message Object is transferred to the IFx Data Register before the CPU writes the new data bytes.
When only the (eight) data bytes are updated, first 0x0087 is written to the Command Mask Register and then the number of the Message Object is written to the Command Request Register, concurrently updating the data bytes and setting TxRqst with NewDat.
To prevent the reset of TxRqst at the end of a transmission that may already be in progress while the data is updated, NewDat has to be set together with TxRqst in event driven CAN communication. For details see section 4.1.2.
When NewDat is set together with TxRqst, NewDat will be reset as soon as the new transmission has started.
BOSCH | - 57/77 - | 11.11.02 |
