Example for Bit Timing at high Baudrate | Bosch Appliances TTCAN

TTCAN

User’s Manual

Revision 1.6

If more than one conﬁguration is possible, that conﬁguration allowing the highest oscillator tolerance range should be chosen.

CAN nodes with different system clocks require different conﬁgurations to come to the same bit rate. The calculation of the propagation time in the CAN network, based on the nodes with the longest delay times, is done once for the whole network.

The CAN system’s oscillator tolerance range is limited by that node with the lowest tolerance range.

The calculation may show that bus length or bit rate have to be decreased or that the oscillator frequencies’ stability has to be increased in order to ﬁnd a protocol compliant conﬁguration of the CAN bit timing.

The resulting conﬁguration is written into the Bit Timing Register:

(Phase_Seg2-1)&(Phase_Seg1+Prop_Seg-1)&(SynchronisationJumpWidth-1)&(Prescaler-1)

4.2.1.7 Example for Bit Timing at high Baudrate

In this example, the frequency of CAN_CLK is 10 MHz, BRP is 0, the bit rate is 1 MBit/s.

tq	100	ns	=	tCAN_CLK
delay of bus driver	50	ns
delay of receiver circuit	30	ns
delay of bus line (40m)	220	ns
tProp	600	ns	=	6 • tq
tSJW	100	ns	=	1 • tq
tTSeg1	700	ns	=	tProp + tSJW
tTSeg2	200	ns	=	Information Processing Time + 1 • tq
tSync-Seg	100	ns	=	1 • tq
bit time	1000	ns	=	tSync-Seg + tTSeg1 + tTSeg2

tolerance for CAN_CLK 0.39 %

=


		min(PB 1, PB 2)
=	---------------------------------------------------------------
=	2	× (13 × bit time –PB2)
		0.1µs
	-----------------------------------------------------------
	2	× (13 × 1µs –0.2µs)

In this example, the concatenated bit time parameters are (2-1)3&(7-1)4&(1-1)2&(1-1)6, the Bit Timing Register is programmed to= 0x1600.

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Bosch Appliances TTCAN user manual Example for Bit Timing at high Baudrate

Contents

User’s Manual Robert Bosch GmbH Copyright Notice and Proprietary Information Change Control Functional Overview 2.2. Block Diagram Operating ModesConventions Scope References Terms and Abbreviations Can Application Ttcan Configuration Ttcan Schedule InitialisationTtcan Message Handling List of Figures Change Control Current Status Change HistoryConventions Helvetica bold Term Meaning Functional Overview Cpuifc Ttcan Operating Modes Software Initialisation Can Message Transfer Test Mode Disabled Automatic RetransmissionTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back Mode Loop Back combined with Silent Mode No Message RAM Mode Software control of Pin Cantx Address Name Reset Value Hardware Reset Description Ttcan Register Summary CCE DAREIE SIE No Error Status Register addresses 0x03 Status Interrupts Error Counter addresses 0x05Bit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C Direction = Write IFx Command Mask RegistersArb IFx Command Request Registers Direction = ReadControl ClrIntPnd Busy Message NumberIFx Message Buffer Registers IFx Mask Registers IFx Data a and Data B Registers IFx Message Control RegistersMessage Object in the Message Memory ID28-0 Msk28-0Xtd Dir 26/77 11.11.02 Message Handler Registers Interrupt Register addresses 0x09 New Data Registers Transmission Request RegistersInterrupt Pending Registers Message Valid 1 Register 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessTrigger Number TT Operation Mode Register addresses 0x29 TypeTimeMark At CycleCount mod MPr2-0 Rdlc EecsTEW TT Interrupt Enable Register addresses 0x31 CCMBark AppWdL CEL GTEGTW SWE RTO TT Cycle Count Register addresses 0x3D & 0x3C TT Error Level Register addresses 0x3F & 0x3ETUR Numerator Conﬁguration Low Register addresses 0x57 TUR Numerator Actual Registers addresses 0x5B & 0x5A TUR Denominator Conﬁguration Register addresses 0x59TT StopWatch Register addresses 0x61 QCS QgtpEcal Egtf TMC DETECS SWS EPE TMG 40/77 11.11.02 Internal can Message Handling Data Transfer Between IFx Registers and Message RAM Transmission of Messages in Event Driven can Communication Start Acceptance Filtering of Received Messages Reception of Data FrameReception of Remote Frame Storing Received Messages in Fifo Buffers Receive / Transmit Priority Conﬁguration of the Module Sync PropSeg PhaseSeg1 PhaseSeg2 1 Conﬁguration of the Bit TimingBit Time and Bit Rate Canclk input Nominal can Bit Time Propagation Time Segment BRP Phase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes Oscillator Tolerance Range 1.5 Conﬁguration of the can Protocol Controller Calculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate Example for Bit Timing at low Baudrate 2 Conﬁguration of the Message Memory 2.1 Conﬁguration of a Transmit Object for Data Frames 2.2 Conﬁguration of a Single Receive Object for Data Frames 2.3 Conﬁguration of a Fifo Buffer Can Communication Handling of Interrupts Updating a Transmit Object Changing a Transmit Object Reading Received MessagesRequesting New Data for a Receive Object Reading from a Fifo Buffer CPU Handling of a Fifo Buffer Interrupt Driven Ttcan Conﬁguration Ttcan Timing 510 125000 32.5 100/12 529/17 TURMessage Scheduling Trigger Memory 63/77 11.11.02 Reference Message Message ObjectsPeriodic Transmit Message Time Slaves Event Driven Transmit MessagePotential Time Masters Ttcan Message Handling Message Reception Message TransmissionPeriodic Messages Event Driven Messages Ttcan Gap Control Stopwatch Cycle Time and Global Time Synchronisation Ttcan Interrupt and Error Handling Previous RefMark Conﬁguration Example Register Remark Rdlc & TEW & CCM Type & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Interface GenericCustomer Interface Timing of the Wait output signal Canclk CanwaitbBusy = ‘1’ Busy = ‘0’ Interrupt Timing EOF