Intel MultiProcessor specification

THIS SPECIFICATION IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.

A license is hereby granted to copy and reproduce this specification for internal use only.

No other license, express or implied, by estoppel or otherwise, to any other intellectual property rights is granted herein.

Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to implementation of information in this specification. Intel does not warrant or represent that such implementation(s) will not infringe such rights.

Intel Corporation and Intel's FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. or its FASTPATH trademark or products.

* Third-party trademarks are the property of their respective owners.

Additional copies of this document or other Intel literature may be obtained from:

Intel Corporation

Literature Center

P.O. Box 7641

Mt. Prospect IL 60056-7641

or call 800-879-4683

printed on	Copyright © 1993-1997. Intel Corporation, All Rights Reserved.
recycled paper

Image 2

Intel MultiProcessor manual Copyright 1993-1997. Intel Corporation, All Rights Reserved

Contents

MultiProcessor Specification Copyright 1993-1997. Intel Corporation, All Rights Reserved Revision History Revision Revision History DatePage Table of Contents Contents MP Configuration TableDefault Configurations Appendix E Errata Glossary Appendix a System Bios Programming GuidelinesAppendix B Operating System Programming Guidelines Figures Tables Examples Page Goals Conceptual Overview Scope Features of the SpecificationMultiProcessor Specification Document Organization Target AudienceOrganization of This Document Introduction Conventions Used in This Document For More Information System Overview Hardware Overview System Processors Advanced Programmable Interrupt Controller System Overview System Memory 4 I/O Expansion Bus Bios Overview Operating System OverviewPage Hardware Specification System Memory Configuration System Memory Cacheability and Shareability System Memory Address Map Hardware Specification Memory Cacheability Map External Cache Subsystem Locking Apic Architecture Posted Memory WriteMultiprocessor Interrupt Control Interrupt Modes Apic Versions PIC Mode PIC Mode Virtual Wire Mode Virtual Wire Mode via Local Apic Virtual Wire Mode via I/O Apic Symmetric I/O Mode Symmetric I/O Mode Apic Memory Mapping Assignment of System Interrupts to the Apic Local UnitFloating Point Exception Interrupt Apic Interval Timers Apic Identification Reset Support System-wide Reset System-wide Init Processor-specific Init Support for Fault-resilient Booting System Initial State MP Configuration Table MultiProcessor Specification Offset Length Field Bytesbits in bits Description MP Configuration TableMP Floating Pointer Structure Information Byte MP FeatureOffset Length Field Bytesbits Bits Description Information Bytes MP Configuration Table Header MP Configuration Table Header Offset Length Field Bytes Bits Description Base MP Configuration Table EntriesMP Configuration Table Header Fields Length Entry Description Entry Type Code Bytes Comments Base MP Configuration Table Entry TypesProcessor Entries Apic Processor Entry Fields Family Model Stepping a Description Feature Flags from Cpuid InstructionIntel486 and Pentium Processor Signatures Bit Name Description Comments BUS Type Bus EntriesBUS ID String Bus Type String Values Bus Type String Description Apic Entry 3 I/O Apic Entries4 I/O Interrupt Assignment Entries I/O Apic Entry Fields I/O Interrupt Entry 10. I/O Interrupt Entry Fields Interrupt Type Description Comments Local Interrupt Assignment Entries11. Interrupt Type Values Destination Local Apic 12. Local Interrupt Entry FieldsDestination Local Apic ID LINTIN# Extended MP Configuration Table Entries System Address Space Mapping Entries 14. System Address Space Mapping Entry Fields 10. Example System with Multiple Bus Types and Bridge Types Bus Hierarchy Descriptor Entry Compatibility Bus Address Space Modifier Entry 12. Compatibility Bus Address Space Modifier Entry 16. Compatibility Bus Address Space Modifier Entry Fields Default Configurations Default Number Bus Discrete Apic ConfigurationsDefault Configurations Config Code CPUs Type Variant Schematic Default Configuration for Discrete Apic Default Configurations Integrated Apic Configurations Default Configuration for Integrated Apic Assignment of I/O Interrupts to the Apic I/O Unit Default Configuration Interrupt AssignmentsConfig INTINx Comments First I/O Eisa and IRQ13 All Local APICs Config LINTINx CommentsAssignment of System Interrupts to the Apic Local Unit Level-triggered Interrupt Support MultiProcessor Specification System Bios Programming Guidelines Bios Post Initialization Programming the Apic for Virtual Wire Mode Controlling the Application Processors Example A-1. Programming Local Apic for Virtual Wire Mode System Bios Programming Guidelines Constructing the MP Configuration Table NMI System Bios Programming Guidelines Page Operating System Boot-up Operating System Programming Guidelines Operating System Booting and Self-configuration Interrupt Mode Initialization and Handling Application Processor Startup Operating System Programming Guidelines Using Init IPI Using Startup IPI AP Shutdown Handling Handling Cache Flush Other IPI ApplicationsSpurious Apic Interrupts Handling TLB Invalidation Supporting Unequal Processors Page System Compliance Checklist Page Interrupt Routing with Multiple APICs Variable Interrupt Routing Fixed Interrupt Routing Multiple I/O Apic Multiple PCI Bus Systems Bus Entries in Systems with More Than One PCI BusI/O Interrupt Assignment Entries for PCI Devices INTD#Page Errata 126 System Address Space Mapping Entries System Address Space Entry Address Type 14. System Address Space Mapping Entry FieldsEntry Length Address Base Bus Hierarchy Descriptor Entry Space records must also be provided BUS Informationsd Parent BUS Glossary Glossary-2 Order Number