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Intel MultiProcessor manual 4.3.3 I/O APIC Entries, 4.3.4 I/O Interrupt Assignment Entries

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4.3.3 I/O APIC Entries

MultiProcessor Specification

4.3.3 I/O APIC Entries

The configuration table contains one or more entries for I/O APICs. Figure 4-6 shows the format of each I/O APIC entry, and Table 4-9 explains each field.

31	24 23		16	15	8	7	0
	MEMORY-MAPPED ADDRESS OF I/O APIC

I/O APIC FLAGS			I/O APIC		I/O APIC ID		ENTRY TYPE
	E		VERSION #		I/O APIC ID		2
RESERVED	N
31	24 23		16	15	8	7	0

04H

00H

	Figure 4-6.		I/O APIC Entry
Table 4-9. I/O APIC Entry Fields

	Offset	Length
Field	(in bytes:bits)	(in bits)	Description

ENTRY TYPE	0	8	A value of 2 identifies an I/O APIC entry.

I/O APIC ID	1	8	The ID of this I/O APIC.

I/O APIC VERSION #	2	8	Bits 0–7 of the I/O APIC’s version register.

I/O APIC FLAGS: EN	3:0	1	If zero, this I/O APIC is unusable, and the
			operating system should not attempt to access
			this I/O APIC.
			At least one I/O APIC must be enabled.

I/O APIC ADDRESS	4	32	Base address for this I/O APIC.

4.3.4 I/O Interrupt Assignment Entries

These entries indicate which interrupt source is connected to each I/O APIC interrupt input. There is one entry for each I/O APIC interrupt input that is connected. Figure 4-7 shows the format of each entry, and Table 4-10 explains each field. Appendix D provides the semantics for encoding PCI interrupts.

The MP specification enables significantly more interrupt sources than the standard AT architecture by using I/O APICs. When using I/O APICs, it is preferable that the buses do not share interrupts with the other buses. Bus implementations that share interrupts, such as the PCI and VL local buses, support their bus interrupts by overloading them into another bus space. These buses can be supported in one of the following two ways:

1.Interrupt Assignment Entries for each of the bus interrupts are listed in the MP configuration table. Each interrupt destination matches the destination of another interrupt source interrupt that this interrupt shares. For example, if PCI-Device1/INTA# has the same vector as ISA-IRQ2, then both Interrupt Assignment Entries for these vectors would refer to the same destination I/O APIC and INTIN#.

4-12	Version 1.4

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Intel MultiProcessor manual 4.3.3 I/O APIC Entries, 4.3.4 I/O Interrupt Assignment Entries, I/O APIC Entry

Contents

MultiProcessor Specification VersionIntel Corporation Literature Center P.O. Box Revision History RevisionRevision History DatePage Table of Contents Chapter 3 Hardware SpecificationChapter 1 Introduction Chapter 2 System OverviewChapter 4 MP Configuration Table Chapter 5 Default ConfigurationsAppendix A System BIOS Programming Guidelines Appendix C System Compliance ChecklistAppendix E Errata Glossary Figures TablesExamples Page 1 Introduction 1.1 Goals1.2 Features of the Specification 1.3Scope1.4 Target Audience 1.5Organization of This DocumentIS EXPECTED TO REMAIN CONSTANT 1.6 Conventions Used in This Document 1.7 For More InformationIN THE RESERVED FIELDS 2 System Overview Version2.1 Hardware Overview 2.1.1System ProcessorsFigure 2-2.APIC Configuration 2.1.2Advanced Programmable Interrupt Controller2.1.3System Memory 2.1.4I/O Expansion Bus2.2 BIOS Overview 2.3 Operating System OverviewPage 3 Hardware Specification 3.1 System Memory Configuration3.2 System Memory Cacheability and Shareability Figure 3-1.System Memory Address MapHardware Specification Table 3-1.Memory Cacheability MapAddresses Shared by All3.3 External Cache Subsystem 3.4Locking3.5 Posted Memory Write 3.6 Multiprocessor Interrupt Control3.6.1APIC Architecture 3.6.2Interrupt Modes 3.6.2.1PIC Mode VersionFigure 3-2.PIC Mode 3.6.2.2Virtual Wire Mode Figure 3-3.Virtual Wire Mode via Local APICFigure 3-4.Virtual Wire Mode via I/O APIC 3-103.6.2.3Symmetric I/O Mode Figure 3-5.Symmetric I/O Mode3.6.4Floating Point Exception Interrupt 3.6.5APIC Memory Mapping3.6.7APIC Interval Timers 3.6.8Multiple I/O APIC Configurations3.6.6APIC Identification 3.7 RESET Support 3.7.1System-wideRESET3.7.2System-wideINIT 3.7.3Processor-specificINITVersion 3-153.9 Support for Fault-resilientBooting 3.8 System Initial State4 MP Configuration Table Figure 4-1.MP Configuration Data StructuresThe following two data structures are used 4.1MP Floating Pointer Structure Figure 4-2.MP Floating Pointer StructureTable 4-1.MP Floating Pointer Structure Fields MultiProcessor Specification OffsetLength Field4.2MP Configuration Table Header Figure 4-3.MP Configuration Table Header1CH 10H 4.3BaseMP Configuration Table Entries ENTRY TYPETable 4-3. BaseMP Configuration TableEntry Types 4.3.1Processor EntriesFigure 4-4.Processor Entry Table 4-4.Processor Entry Fields Table 4-6.Feature Flags from CPUID Instruction MP Configuration TableFamily Model4.3.2 Bus Entries Figure 4-5.Bus Entry Table 4-7.Bus Entry FieldsMP Configuration Table Table 4-8.Bus Type String ValuesBus Type String Description4.3.3 I/O APIC Entries 4.3.4 I/O Interrupt Assignment EntriesI/O APIC Entry Table 4-9.I/O APIC Entry FieldsFigure 4-7.I/O Interrupt Entry Version4-13 Table 4-10.I/O Interrupt Entry Fields 4.3.5Local Interrupt Assignment Entries Table 4-11.Interrupt Type ValuesFigure 4-8.Local Interrupt Entry MultiProcessor Specification Table 4-12.Local Interrupt Entry FieldsOffset in Length4.4Extended MP Configuration Table Entries 4.4.1System Address Space Mapping Entries Figure 4-9.System Address Space EntryMP Configuration Table OffsetLength FieldSince all device settings must fall within supported System Address Space mapping for a given bus in order to be usable by the operating system, buses that do not support dynamically configurable devices i.e., ISA, EISA should support all possible addresses to that bus 4.4.2Bus Hierarchy Descriptor Entry Figure 4-11.Bus Hierarchy Descriptor EntryTable 4-15Bus Hierarchy Descriptor Entry Fields OffsetLength FieldVersion 4-23PREDEFINED RANGE LIST ADDRESS MODTable 4-17.Predefined Range Lists 5 Default Configurations 5.1 Discrete APIC Configurations Table 5-1.Default ConfigurationsDefault Configurations VersionSHADED AREAS MARK5.2 Integrated APIC Configurations Version SHADED AREASB,C EISA BUS SPECIFIC D PCI BUS SPECIFIC MARKMultiProcessor Specification 5.3.1EISA and IRQ13 5.3.2Level-triggeredInterrupt SupportThe 8259A INTR output signal is connected to the LINTIN0 of all local APICs, which makes INTR dynamically routable via software. NMI is connected to the LINTIN1 of all local APICs, which makes NMI dynamically routable via software A System BIOS Programming Guidelines A.1 BIOS Post InitializationA.3 Programming the APIC for Virtual Wire Mode A.2 Controlling the Application ProcessorsSystem BIOS Programming Guidelines VersionA.4 Constructing the MP Configuration Table Version Page B Operating System Programming Guidelines B.1 Operating System Boot-upB.3 Interrupt Mode Initialization and Handling B.4 Application Processor Startup Example B-1.Universal Start-upAlgorithmB.4.1 USINGINIT IPI B.4.2 USINGSTARTUP IPI B.5 APShutdown HandlingB.6 Other IPI Applications B.7 Spurious APIC InterruptsB.6.1 Handling Cache Flush B.6.2 Handling TLB InvalidationB.8 Supporting Unequal Processors VersionPage C System Compliance Checklist Any NO answer indicates non-complianceCondition Page D Multiple I/O APIC Multiple PCI Bus Systems D.1 Interrupt Routing with Multiple APICsD.1.1 Variable Interrupt Routing D.1.2 Fixed Interrupt Routing Multiple I/O APIC Multiple PCI Bus Systems OffsetLength FieldPage E Errata VersionSIGNATURE 4.4.1 System Address Space Mapping Entries Figure 4-9.System Address Space EntryENTRY TYPE 4.4.2 Bus Hierarchy Descriptor Entry space records must also be providedFigure 4-11.Bus Hierarchy Descriptor Entry Table 4-15Bus Hierarchy Descriptor Entry FieldsGlossary Glossary-2 Order Number