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Intel MultiProcessor System Memory Cacheability and Shareability, 1.System Memory Address Map

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Figure 3-1. System Memory Address Map

MultiProcessor Specification

4GB

FFFF_FFFFH

FFFE_0000H

FEF0_0000H

FEE0_0000H

FED0_0000H

FEC0_0000H

1MB 0010_0000H

000F_0000H

000E_0000H

000D_0000H

000C_0000H

640K 000A_0000H

0000_0000H

BIOS PROM

LOCAL APIC

I/O APIC

MEMORY-MAPPED

I/O SPACE

EXTENDED

MEMORY REGION

SHADOWED BIOS

SHADOWED

EXPANSION BIOS

EXPANSION ROM

ROM EXTENSIONS

VIDEO BUFFER

SYSTEM-BASED

MEMORY

PART OF THIS SPECIFICATION

UNSHADED ADDRESS REGIONS ARE FOR REFERENCE ONLY AND SHOULD NOT BE CONSTRUED AS THE SOLE DEFINITION OF A PC/AT-COMPATIBLE ADDRESS SPACE.

Figure 3-1. System Memory Address Map

3.2 System Memory Cacheability and Shareability

The cacheability and shareability of the physical memory space are defined in Table 3-1. The address space reserved for the local APIC is used by each processor to access its own local APIC. The address space reserved for the I/O APIC must be shareable by all processors to permit dynamic reconfiguration.

3-2	Version 1.4

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Intel MultiProcessor manual System Memory Cacheability and Shareability, 1.System Memory Address Map

Contents

MultiProcessor Specification VersionIntel Corporation Literature Center P.O. Box Revision History Revision HistoryRevision DatePage Chapter 1 Introduction Table of ContentsChapter 3 Hardware Specification Chapter 2 System OverviewChapter 4 MP Configuration Table Chapter 5 Default ConfigurationsAppendix C System Compliance Checklist Appendix A System BIOS Programming GuidelinesAppendix E Errata Glossary Figures TablesExamples Page 1 Introduction 1.1 Goals1.2 Features of the Specification 1.3Scope1.5Organization of This Document 1.4 Target AudienceIS EXPECTED TO REMAIN CONSTANT 1.7 For More Information 1.6 Conventions Used in This DocumentIN THE RESERVED FIELDS 2 System Overview Version2.1 Hardware Overview 2.1.1System ProcessorsFigure 2-2.APIC Configuration 2.1.2Advanced Programmable Interrupt Controller2.1.3System Memory 2.1.4I/O Expansion Bus2.2 BIOS Overview 2.3 Operating System OverviewPage 3 Hardware Specification 3.1 System Memory Configuration3.2 System Memory Cacheability and Shareability Figure 3-1.System Memory Address MapAddresses Hardware SpecificationTable 3-1.Memory Cacheability Map Shared by All3.3 External Cache Subsystem 3.4Locking3.6 Multiprocessor Interrupt Control 3.5 Posted Memory Write3.6.1APIC Architecture 3.6.2Interrupt Modes 3.6.2.1PIC Mode VersionFigure 3-2.PIC Mode 3.6.2.2Virtual Wire Mode Figure 3-3.Virtual Wire Mode via Local APICFigure 3-4.Virtual Wire Mode via I/O APIC 3-103.6.2.3Symmetric I/O Mode Figure 3-5.Symmetric I/O Mode3.6.4Floating Point Exception Interrupt 3.6.5APIC Memory Mapping3.6.8Multiple I/O APIC Configurations 3.6.7APIC Interval Timers3.6.6APIC Identification 3.7 RESET Support 3.7.1System-wideRESETVersion 3.7.2System-wideINIT3.7.3Processor-specificINIT 3-153.9 Support for Fault-resilientBooting 3.8 System Initial State4 MP Configuration Table Figure 4-1.MP Configuration Data StructuresThe following two data structures are used Figure 4-2.MP Floating Pointer Structure 4.1MP Floating Pointer StructureTable 4-1.MP Floating Pointer Structure Fields Length MultiProcessor SpecificationOffset FieldFigure 4-3.MP Configuration Table Header 4.2MP Configuration Table Header1CH 10H 4.3BaseMP Configuration Table Entries ENTRY TYPE4.3.1Processor Entries Table 4-3. BaseMP Configuration TableEntry TypesFigure 4-4.Processor Entry Table 4-4.Processor Entry Fields Family Table 4-6.Feature Flags from CPUID InstructionMP Configuration Table Model4.3.2 Bus Entries Figure 4-5.Bus Entry Table 4-7.Bus Entry FieldsBus Type String MP Configuration TableTable 4-8.Bus Type String Values DescriptionI/O APIC Entry 4.3.3 I/O APIC Entries4.3.4 I/O Interrupt Assignment Entries Table 4-9.I/O APIC Entry FieldsVersion Figure 4-7.I/O Interrupt Entry4-13 Table 4-10.I/O Interrupt Entry Fields Table 4-11.Interrupt Type Values 4.3.5Local Interrupt Assignment EntriesFigure 4-8.Local Interrupt Entry Offset in MultiProcessor SpecificationTable 4-12.Local Interrupt Entry Fields Length4.4Extended MP Configuration Table Entries 4.4.1System Address Space Mapping Entries Figure 4-9.System Address Space EntryLength MP Configuration TableOffset FieldSince all device settings must fall within supported System Address Space mapping for a given bus in order to be usable by the operating system, buses that do not support dynamically configurable devices i.e., ISA, EISA should support all possible addresses to that bus 4.4.2Bus Hierarchy Descriptor Entry Figure 4-11.Bus Hierarchy Descriptor EntryLength Table 4-15Bus Hierarchy Descriptor Entry FieldsOffset FieldPREDEFINED RANGE LIST Version4-23 ADDRESS MODTable 4-17.Predefined Range Lists 5 Default Configurations 5.1 Discrete APIC Configurations Table 5-1.Default ConfigurationsSHADED AREAS Default ConfigurationsVersion MARK5.2 Integrated APIC Configurations B,C EISA BUS SPECIFIC D PCI BUS SPECIFIC VersionSHADED AREAS MARKMultiProcessor Specification 5.3.1EISA and IRQ13 5.3.2Level-triggeredInterrupt SupportThe 8259A INTR output signal is connected to the LINTIN0 of all local APICs, which makes INTR dynamically routable via software. NMI is connected to the LINTIN1 of all local APICs, which makes NMI dynamically routable via software A System BIOS Programming Guidelines A.1 BIOS Post InitializationA.3 Programming the APIC for Virtual Wire Mode A.2 Controlling the Application ProcessorsSystem BIOS Programming Guidelines VersionA.4 Constructing the MP Configuration Table Version Page B Operating System Programming Guidelines B.1 Operating System Boot-upB.3 Interrupt Mode Initialization and Handling B.4 Application Processor Startup Example B-1.Universal Start-upAlgorithmB.4.1 USINGINIT IPI B.4.2 USINGSTARTUP IPI B.5 APShutdown HandlingB.6.1 Handling Cache Flush B.6 Other IPI ApplicationsB.7 Spurious APIC Interrupts B.6.2 Handling TLB InvalidationB.8 Supporting Unequal Processors VersionPage Any NO answer indicates non-compliance C System Compliance ChecklistCondition Page D.1 Interrupt Routing with Multiple APICs D Multiple I/O APIC Multiple PCI Bus SystemsD.1.1 Variable Interrupt Routing D.1.2 Fixed Interrupt Routing Length Multiple I/O APIC Multiple PCI Bus SystemsOffset FieldPage E Errata VersionSIGNATURE 4.4.1 System Address Space Mapping Entries Figure 4-9.System Address Space EntryENTRY TYPE 4.4.2 Bus Hierarchy Descriptor Entry space records must also be providedFigure 4-11.Bus Hierarchy Descriptor Entry Table 4-15Bus Hierarchy Descriptor Entry FieldsGlossary Glossary-2 Order Number