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Intel MultiProcessor manual Default Configurations, Version, Shaded Areas, Mark

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Default Configurations

Default Configurations

A

IMCR

E0

BSP

INTEL486™

CPU 1

NMI INTR RESET

AP2

INTEL486™

CPU 3

NMI INTR RESET

	PNMI		PINT		PRST ExtINTA		PNMI	PINT		PRST ExtINTA
			LOCAL					LOCAL
REG.		82489DX APIC				INTA	82489DX APIC						INTA
MARK	LINTIN0			LINTIN1		TRAP	LINTIN0		LINTIN1				TRAP
	LINTIN0			LINTIN1			LINTIN0		LINTIN1
NMI
INTR
RESET
ICC BUS
I/O BUS
NMI
IRQ1										0
										1
B						3				2
B						3				3
8254 TIMER						4				3
						4				4
						5				4
						5				5
						6				5			I/O
						6				6
						7				6
IRQ8#			8			7				7	82489DX
IRQ8#			8							7	82489DX
						9				8		APIC
						9				9		APIC
						10				10
						11				10
						11				11
IRQ13										11
IRQ13					13					12
					13					13
						14				13
C						14				14
						15				14
						15				15
EISA DMA CHAINING										15
EISA DMA CHAINING														GLUE
														GLUE
FROM BSP
FERR#	FERR									0
IGNNE#	FERR
	SAMPLING
	SAMPLING									1
						3				32	MASTER			INTR
						4				4	8259A PIC
						5				4	8259A PIC
						5				5
						6				5
ABFULL	ABFULL					6				6
						7				6
					12	7				7
(PS/2 MOUSE) SAMPLING					12
(PS/2 MOUSE) SAMPLING													INTA
													INTA
D										0
EDGE/LEVEL TRIGGER						9				0
EDGE/LEVEL TRIGGER						9				1
POLARITY CONTROL						10				1
						10				2
						11				2		SLAVE
IRQ3-7,										3		SLAVE
IRQ3-7,	IRQx									4	8259A PIC
9-12,14,15	IRQx					14				5
	LITMx					14				6
LITM3-7,			12			15				6
						15				7
										7
9-12,14,15

SHADED AREAS:

A: OPTIONAL IF VIRTUAL WIRE MODE IS IMPLEMENTED

B,C: MAY NOT BE EXTERNALIZED WITH SOME EISA CHIPSETS

C,D: EISA BUS SPECIFIC

Figure 5-1. Default Configuration for Discrete APIC

Version 1.4

5-3

Image 63

Intel MultiProcessor manual Default Configurations, Version, Shaded Areas, Mark

Contents

Version MultiProcessor SpecificationIntel Corporation Literature Center P.O. Box Date Revision HistoryRevision Revision HistoryPage Chapter 2 System Overview Table of ContentsChapter 3 Hardware Specification Chapter 1 IntroductionChapter 5 Default Configurations Chapter 4 MP Configuration TableAppendix A System BIOS Programming Guidelines Appendix C System Compliance ChecklistAppendix E Errata Glossary Tables FiguresExamples Page 1.1 Goals 1 Introduction1.3Scope 1.2 Features of the Specification1.4 Target Audience 1.5Organization of This DocumentIS EXPECTED TO REMAIN CONSTANT 1.6 Conventions Used in This Document 1.7 For More InformationIN THE RESERVED FIELDS Version 2 System Overview2.1.1System Processors 2.1 Hardware Overview2.1.2Advanced Programmable Interrupt Controller Figure 2-2.APIC Configuration2.1.4I/O Expansion Bus 2.1.3System Memory2.3 Operating System Overview 2.2 BIOS OverviewPage 3.1 System Memory Configuration 3 Hardware SpecificationFigure 3-1.System Memory Address Map 3.2 System Memory Cacheability and ShareabilityShared by All Hardware SpecificationTable 3-1.Memory Cacheability Map Addresses3.4Locking 3.3 External Cache Subsystem3.5 Posted Memory Write 3.6 Multiprocessor Interrupt Control3.6.1APIC Architecture 3.6.2Interrupt Modes Version 3.6.2.1PIC ModeFigure 3-2.PIC Mode Figure 3-3.Virtual Wire Mode via Local APIC 3.6.2.2Virtual Wire Mode3-10 Figure 3-4.Virtual Wire Mode via I/O APICFigure 3-5.Symmetric I/O Mode 3.6.2.3Symmetric I/O Mode3.6.5APIC Memory Mapping 3.6.4Floating Point Exception Interrupt3.6.7APIC Interval Timers 3.6.8Multiple I/O APIC Configurations3.6.6APIC Identification 3.7.1System-wideRESET 3.7 RESET Support3-15 3.7.2System-wideINIT3.7.3Processor-specificINIT Version3.8 System Initial State 3.9 Support for Fault-resilientBootingFigure 4-1.MP Configuration Data Structures 4 MP Configuration TableThe following two data structures are used 4.1MP Floating Pointer Structure Figure 4-2.MP Floating Pointer StructureTable 4-1.MP Floating Pointer Structure Fields Field MultiProcessor SpecificationOffset Length4.2MP Configuration Table Header Figure 4-3.MP Configuration Table Header1CH 10H ENTRY TYPE 4.3BaseMP Configuration Table EntriesTable 4-3. BaseMP Configuration TableEntry Types 4.3.1Processor EntriesFigure 4-4.Processor Entry Table 4-4.Processor Entry Fields Model Table 4-6.Feature Flags from CPUID InstructionMP Configuration Table FamilyFigure 4-5.Bus Entry Table 4-7.Bus Entry Fields 4.3.2 Bus EntriesDescription MP Configuration TableTable 4-8.Bus Type String Values Bus Type StringTable 4-9.I/O APIC Entry Fields 4.3.3 I/O APIC Entries4.3.4 I/O Interrupt Assignment Entries I/O APIC EntryFigure 4-7.I/O Interrupt Entry Version4-13 Table 4-10.I/O Interrupt Entry Fields 4.3.5Local Interrupt Assignment Entries Table 4-11.Interrupt Type ValuesFigure 4-8.Local Interrupt Entry Length MultiProcessor SpecificationTable 4-12.Local Interrupt Entry Fields Offset in4.4Extended MP Configuration Table Entries Figure 4-9.System Address Space Entry 4.4.1System Address Space Mapping EntriesField MP Configuration TableOffset LengthSince all device settings must fall within supported System Address Space mapping for a given bus in order to be usable by the operating system, buses that do not support dynamically configurable devices i.e., ISA, EISA should support all possible addresses to that bus Figure 4-11.Bus Hierarchy Descriptor Entry 4.4.2Bus Hierarchy Descriptor EntryField Table 4-15Bus Hierarchy Descriptor Entry FieldsOffset LengthADDRESS MOD Version4-23 PREDEFINED RANGE LISTTable 4-17.Predefined Range Lists 5 Default Configurations Table 5-1.Default Configurations 5.1 Discrete APIC ConfigurationsMARK Default ConfigurationsVersion SHADED AREAS5.2 Integrated APIC Configurations MARK VersionSHADED AREAS B,C EISA BUS SPECIFIC D PCI BUS SPECIFICMultiProcessor Specification 5.3.2Level-triggeredInterrupt Support 5.3.1EISA and IRQ13The 8259A INTR output signal is connected to the LINTIN0 of all local APICs, which makes INTR dynamically routable via software. NMI is connected to the LINTIN1 of all local APICs, which makes NMI dynamically routable via software A.1 BIOS Post Initialization A System BIOS Programming GuidelinesA.2 Controlling the Application Processors A.3 Programming the APIC for Virtual Wire ModeVersion System BIOS Programming GuidelinesA.4 Constructing the MP Configuration Table Version Page B.1 Operating System Boot-up B Operating System Programming GuidelinesB.3 Interrupt Mode Initialization and Handling Example B-1.Universal Start-upAlgorithm B.4 Application Processor StartupB.4.1 USINGINIT IPI B.5 APShutdown Handling B.4.2 USINGSTARTUP IPIB.6.2 Handling TLB Invalidation B.6 Other IPI ApplicationsB.7 Spurious APIC Interrupts B.6.1 Handling Cache FlushVersion B.8 Supporting Unequal ProcessorsPage C System Compliance Checklist Any NO answer indicates non-complianceCondition Page D Multiple I/O APIC Multiple PCI Bus Systems D.1 Interrupt Routing with Multiple APICsD.1.1 Variable Interrupt Routing D.1.2 Fixed Interrupt Routing Field Multiple I/O APIC Multiple PCI Bus SystemsOffset LengthPage Version E ErrataSIGNATURE Figure 4-9.System Address Space Entry 4.4.1 System Address Space Mapping EntriesENTRY TYPE space records must also be provided 4.4.2 Bus Hierarchy Descriptor EntryTable 4-15Bus Hierarchy Descriptor Entry Fields Figure 4-11.Bus Hierarchy Descriptor EntryGlossary Glossary-2 Order Number