Default Configuration for Discrete Apic | Intel MultiProcessor

Default Configurations

A

IMCR

E0

BSP

INTEL486™

CPU 1

NMI INTR RESET

AP2

INTEL486™

CPU 3

NMI INTR RESET

	PNMI		PINT		PRST ExtINTA		PNMI	PINT		PRST ExtINTA
			LOCAL					LOCAL
REG.		82489DX APIC				INTA	82489DX APIC						INTA
MARK	LINTIN0			LINTIN1		TRAP	LINTIN0		LINTIN1				TRAP
	LINTIN0			LINTIN1			LINTIN0		LINTIN1
NMI
INTR
RESET
ICC BUS
I/O BUS
NMI
IRQ1										0
										1
B						3				2
B						3				3
8254 TIMER						4				3
						4				4
						5				4
						5				5
						6				5			I/O
						6				6
						7				6
IRQ8#			8			7				7	82489DX
IRQ8#			8							7	82489DX
						9				8		APIC
						9				9		APIC
						10				10
						11				10
						11				11
IRQ13										11
IRQ13					13					12
					13					13
						14				13
C						14				14
						15				14
						15				15
EISA DMA CHAINING										15
EISA DMA CHAINING														GLUE
														GLUE
FROM BSP
FERR#	FERR									0
IGNNE#	FERR
	SAMPLING
	SAMPLING									1
						3				32	MASTER			INTR
						4				4	8259A PIC
						5				4	8259A PIC
						5				5
						6				5
ABFULL	ABFULL					6				6
						7				6
					12	7				7
(PS/2 MOUSE) SAMPLING					12
(PS/2 MOUSE) SAMPLING													INTA
													INTA
D										0
EDGE/LEVEL TRIGGER						9				0
EDGE/LEVEL TRIGGER						9				1
POLARITY CONTROL						10				1
						10				2
						11				2		SLAVE
IRQ3-7,										3		SLAVE
IRQ3-7,	IRQx									4	8259A PIC
9-12,14,15	IRQx					14				5
	LITMx					14				6
LITM3-7,			12			15				6
						15				7
										7
9-12,14,15

SHADED AREAS:

A: OPTIONAL IF VIRTUAL WIRE MODE IS IMPLEMENTED

B,C: MAY NOT BE EXTERNALIZED WITH SOME EISA CHIPSETS

C,D: EISA BUS SPECIFIC

Figure 5-1. Default Configuration for Discrete APIC

Version 1.4

5-3

Image 63

Intel MultiProcessor manual Default Configuration for Discrete Apic, Default Configurations

Contents

MultiProcessor Specification Copyright 1993-1997. Intel Corporation, All Rights Reserved Revision Revision History Date Revision HistoryPage Table of Contents MP Configuration Table Default ConfigurationsContents Appendix a System Bios Programming Guidelines Appendix B Operating System Programming GuidelinesAppendix E Errata Glossary Tables Figures Examples Page Conceptual Overview Goals Features of the Specification MultiProcessor SpecificationScope Introduction Target AudienceOrganization of This Document Document Organization For More Information Conventions Used in This Document System Overview System Processors Hardware Overview System Overview Advanced Programmable Interrupt Controller 4 I/O Expansion Bus System Memory Operating System Overview Bios OverviewPage System Memory Configuration Hardware Specification System Memory Address Map System Memory Cacheability and Shareability Memory Cacheability Map Hardware Specification Locking External Cache Subsystem Posted Memory Write Multiprocessor Interrupt ControlApic Architecture Apic Versions Interrupt Modes PIC Mode PIC Mode Virtual Wire Mode via Local Apic Virtual Wire Mode Virtual Wire Mode via I/O Apic Symmetric I/O Mode Symmetric I/O Mode Assignment of System Interrupts to the Apic Local Unit Floating Point Exception InterruptApic Memory Mapping Apic Identification Apic Interval Timers System-wide Reset Reset Support Processor-specific Init System-wide Init System Initial State Support for Fault-resilient Booting MP Configuration Table MultiProcessor Specification MP Configuration Table MP Floating Pointer StructureOffset Length Field Bytesbits in bits Description Information Bytes MP FeatureOffset Length Field Bytesbits Bits Description Information Byte MP Configuration Table Header MP Configuration Table Header Base MP Configuration Table Entries MP Configuration Table Header FieldsOffset Length Field Bytes Bits Description Apic Base MP Configuration Table Entry TypesProcessor Entries Length Entry Description Entry Type Code Bytes Comments Processor Entry Fields Bit Name Description Comments Feature Flags from Cpuid InstructionIntel486 and Pentium Processor Signatures Family Model Stepping a Description String Bus EntriesBUS ID BUS Type Bus Type String Description Bus Type String Values I/O Apic Entry Fields 3 I/O Apic Entries4 I/O Interrupt Assignment Entries Apic Entry I/O Interrupt Entry 10. I/O Interrupt Entry Fields Local Interrupt Assignment Entries 11. Interrupt Type ValuesInterrupt Type Description Comments LINTIN# 12. Local Interrupt Entry FieldsDestination Local Apic ID Destination Local Apic Extended MP Configuration Table Entries System Address Space Mapping Entries 14. System Address Space Mapping Entry Fields 10. Example System with Multiple Bus Types and Bridge Types Bus Hierarchy Descriptor Entry Compatibility Bus Address Space Modifier Entry 12. Compatibility Bus Address Space Modifier Entry 16. Compatibility Bus Address Space Modifier Entry Fields Default Configurations Config Code CPUs Type Variant Schematic Discrete Apic ConfigurationsDefault Configurations Default Number Bus Default Configurations Default Configuration for Discrete Apic Integrated Apic Configurations Default Configuration for Integrated Apic First I/O Default Configuration Interrupt AssignmentsConfig INTINx Comments Assignment of I/O Interrupts to the Apic I/O Unit Level-triggered Interrupt Support All Local APICs Config LINTINx CommentsAssignment of System Interrupts to the Apic Local Unit Eisa and IRQ13 MultiProcessor Specification Bios Post Initialization System Bios Programming Guidelines Controlling the Application Processors Programming the Apic for Virtual Wire Mode System Bios Programming Guidelines Example A-1. Programming Local Apic for Virtual Wire Mode NMI Constructing the MP Configuration Table System Bios Programming Guidelines Page Operating System Programming Guidelines Operating System Boot-up Interrupt Mode Initialization and Handling Operating System Booting and Self-configuration Operating System Programming Guidelines Application Processor Startup Using Init IPI AP Shutdown Handling Using Startup IPI Handling TLB Invalidation Other IPI ApplicationsSpurious Apic Interrupts Handling Cache Flush Supporting Unequal Processors Page System Compliance Checklist Page Variable Interrupt Routing Interrupt Routing with Multiple APICs Fixed Interrupt Routing INTD# Bus Entries in Systems with More Than One PCI BusI/O Interrupt Assignment Entries for PCI Devices Multiple I/O Apic Multiple PCI Bus SystemsPage Errata 126 System Address Space Entry System Address Space Mapping Entries Address Base 14. System Address Space Mapping Entry FieldsEntry Length Address Type Space records must also be provided Bus Hierarchy Descriptor Entry Parent BUS BUS Informationsd Glossary Glossary-2 Order Number