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MultiProcessor manual
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Specs
MP Configuration Table
3.6.2.2Virtual Wire Mode
RESET Support
Support for Fault-resilientBooting
3.6.7APIC Interval Timers
The 8259A INTR output signal is connected to the LINTIN0 of all local APICs, which makes INTR dynamically routable via software. NMI is connected to the LINTIN1 of all local APICs, which makes NMI dynamically routable via software
Checklist
BIOS Overview
6.Feature Flags from CPUID Instruction
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Contents
MultiProcessor Specification
Version
Intel Corporation Literature Center P.O. Box
Revision History
Revision History
Revision
Date
Page
Chapter 1 Introduction
Table of Contents
Chapter 3 Hardware Specification
Chapter 2 System Overview
Chapter 4 MP Configuration Table
Chapter 5 Default Configurations
Appendix C System Compliance Checklist
Appendix A System BIOS Programming Guidelines
Appendix E Errata Glossary
Figures
Tables
Examples
Page
1 Introduction
1.1 Goals
1.2 Features of the Specification
1.3Scope
1.5Organization of This Document
1.4 Target Audience
IS EXPECTED TO REMAIN CONSTANT
1.7 For More Information
1.6 Conventions Used in This Document
IN THE RESERVED FIELDS
2 System Overview
Version
2.1 Hardware Overview
2.1.1System Processors
Figure 2-2.APIC Configuration
2.1.2Advanced Programmable Interrupt Controller
2.1.3System Memory
2.1.4I/O Expansion Bus
2.2 BIOS Overview
2.3 Operating System Overview
Page
3 Hardware Specification
3.1 System Memory Configuration
3.2 System Memory Cacheability and Shareability
Figure 3-1.System Memory Address Map
Addresses
Hardware Specification
Table 3-1.Memory Cacheability Map
Shared by All
3.3 External Cache Subsystem
3.4Locking
3.6 Multiprocessor Interrupt Control
3.5 Posted Memory Write
3.6.1APIC Architecture
3.6.2Interrupt Modes
3.6.2.1PIC Mode
Version
Figure 3-2.PIC Mode
3.6.2.2Virtual Wire Mode
Figure 3-3.Virtual Wire Mode via Local APIC
Figure 3-4.Virtual Wire Mode via I/O APIC
3-10
3.6.2.3Symmetric I/O Mode
Figure 3-5.Symmetric I/O Mode
3.6.4Floating Point Exception Interrupt
3.6.5APIC Memory Mapping
3.6.8Multiple I/O APIC Configurations
3.6.7APIC Interval Timers
3.6.6APIC Identification
3.7 RESET Support
3.7.1System-wideRESET
Version
3.7.2System-wideINIT
3.7.3Processor-specificINIT
3-15
3.9 Support for Fault-resilientBooting
3.8 System Initial State
4 MP Configuration Table
Figure 4-1.MP Configuration Data Structures
The following two data structures are used
Figure 4-2.MP Floating Pointer Structure
4.1MP Floating Pointer Structure
Table 4-1.MP Floating Pointer Structure Fields
Length
MultiProcessor Specification
Offset
Field
Figure 4-3.MP Configuration Table Header
4.2MP Configuration Table Header
1CH 10H
4.3BaseMP Configuration Table Entries
ENTRY TYPE
4.3.1Processor Entries
Table 4-3. BaseMP Configuration TableEntry Types
Figure 4-4.Processor Entry
Table 4-4.Processor Entry Fields
Family
Table 4-6.Feature Flags from CPUID Instruction
MP Configuration Table
Model
4.3.2 Bus Entries
Figure 4-5.Bus Entry Table 4-7.Bus Entry Fields
Bus Type String
MP Configuration Table
Table 4-8.Bus Type String Values
Description
I/O APIC Entry
4.3.3 I/O APIC Entries
4.3.4 I/O Interrupt Assignment Entries
Table 4-9.I/O APIC Entry Fields
Version
Figure 4-7.I/O Interrupt Entry
4-13
Table 4-10.I/O Interrupt Entry Fields
Table 4-11.Interrupt Type Values
4.3.5Local Interrupt Assignment Entries
Figure 4-8.Local Interrupt Entry
Offset in
MultiProcessor Specification
Table 4-12.Local Interrupt Entry Fields
Length
4.4Extended MP Configuration Table Entries
4.4.1System Address Space Mapping Entries
Figure 4-9.System Address Space Entry
Length
MP Configuration Table
Offset
Field
Since all device settings must fall within supported System Address Space mapping for a given bus in order to be usable by the operating system, buses that do not support dynamically configurable devices i.e., ISA, EISA should support all possible addresses to that bus
4.4.2Bus Hierarchy Descriptor Entry
Figure 4-11.Bus Hierarchy Descriptor Entry
Length
Table 4-15Bus Hierarchy Descriptor Entry Fields
Offset
Field
PREDEFINED RANGE LIST
Version
4-23
ADDRESS MOD
Table 4-17.Predefined Range Lists
5 Default Configurations
5.1 Discrete APIC Configurations
Table 5-1.Default Configurations
SHADED AREAS
Default Configurations
Version
MARK
5.2 Integrated APIC Configurations
B,C EISA BUS SPECIFIC D PCI BUS SPECIFIC
Version
SHADED AREAS
MARK
MultiProcessor Specification
5.3.1EISA and IRQ13
5.3.2Level-triggeredInterrupt Support
The 8259A INTR output signal is connected to the LINTIN0 of all local APICs, which makes INTR dynamically routable via software. NMI is connected to the LINTIN1 of all local APICs, which makes NMI dynamically routable via software
A System BIOS Programming Guidelines
A.1 BIOS Post Initialization
A.3 Programming the APIC for Virtual Wire Mode
A.2 Controlling the Application Processors
System BIOS Programming Guidelines
Version
A.4 Constructing the MP Configuration Table
Version
Page
B Operating System Programming Guidelines
B.1 Operating System Boot-up
B.3 Interrupt Mode Initialization and Handling
B.4 Application Processor Startup
Example B-1.Universal Start-upAlgorithm
B.4.1 USINGINIT IPI
B.4.2 USINGSTARTUP IPI
B.5 APShutdown Handling
B.6.1 Handling Cache Flush
B.6 Other IPI Applications
B.7 Spurious APIC Interrupts
B.6.2 Handling TLB Invalidation
B.8 Supporting Unequal Processors
Version
Page
Any NO answer indicates non-compliance
C System Compliance Checklist
Condition
Page
D.1 Interrupt Routing with Multiple APICs
D Multiple I/O APIC Multiple PCI Bus Systems
D.1.1 Variable Interrupt Routing
D.1.2 Fixed Interrupt Routing
Length
Multiple I/O APIC Multiple PCI Bus Systems
Offset
Field
Page
E Errata
Version
SIGNATURE
4.4.1 System Address Space Mapping Entries
Figure 4-9.System Address Space Entry
ENTRY TYPE
4.4.2 Bus Hierarchy Descriptor Entry
space records must also be provided
Figure 4-11.Bus Hierarchy Descriptor Entry
Table 4-15Bus Hierarchy Descriptor Entry Fields
Glossary
Glossary-2
Order Number
