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Intel MultiProcessor manual MP Configuration Table, 1.MP Configuration Data Structures

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4 MP Configuration Table

4 MP Configuration Table

The operating system must have access to some information about the multiprocessor configuration. The MP specification provides two methods for passing this information to the operating system: a minimal method for configurations that conform to one of a set of common hardware defaults, and a maximal method that provides the utmost flexibility in hardware design. Figure 4-1 shows the general layout of the MP configuration data structures.

31

24 23

16 15

8

7

0

VARIABLE NUMBER OF

VARIABLE-LENGTH

ENTRIES

MP CONFIGURATION TABLE

FLOATING

POINTER

STRUCTURE

ENTRY LENGTH DEPENDS ON ENTRY TYPE

ENTRY TYPE

ENTRY LENGTH DEPENDS ON ENTRY TYPE

ENTRY TYPE

FIXED-LENGT H

HE ADER

31	24 23	16 15	8	7	0
31					0

PHYSICAL ADDRESS POINTER

02CH

0 0 H

Figure 4-1. MP Configuration Data Structures

Version 1.4

4-1

Image 37

Intel MultiProcessor manual MP Configuration Table, 1.MP Configuration Data Structures

Contents

Version MultiProcessor SpecificationIntel Corporation Literature Center P.O. Box Revision Revision HistoryRevision History DatePage Chapter 3 Hardware Specification Table of ContentsChapter 1 Introduction Chapter 2 System OverviewChapter 5 Default Configurations Chapter 4 MP Configuration TableAppendix C System Compliance Checklist Appendix A System BIOS Programming GuidelinesAppendix E Errata Glossary Tables FiguresExamples Page 1.1 Goals 1 Introduction1.3Scope 1.2 Features of the Specification1.5Organization of This Document 1.4 Target AudienceIS EXPECTED TO REMAIN CONSTANT 1.7 For More Information 1.6 Conventions Used in This DocumentIN THE RESERVED FIELDS Version 2 System Overview2.1.1System Processors 2.1 Hardware Overview2.1.2Advanced Programmable Interrupt Controller Figure 2-2.APIC Configuration2.1.4I/O Expansion Bus 2.1.3System Memory2.3 Operating System Overview 2.2 BIOS OverviewPage 3.1 System Memory Configuration 3 Hardware SpecificationFigure 3-1.System Memory Address Map 3.2 System Memory Cacheability and ShareabilityTable 3-1.Memory Cacheability Map Hardware SpecificationAddresses Shared by All3.4Locking 3.3 External Cache Subsystem3.6 Multiprocessor Interrupt Control 3.5 Posted Memory Write3.6.1APIC Architecture 3.6.2Interrupt Modes Version 3.6.2.1PIC ModeFigure 3-2.PIC Mode Figure 3-3.Virtual Wire Mode via Local APIC 3.6.2.2Virtual Wire Mode3-10 Figure 3-4.Virtual Wire Mode via I/O APICFigure 3-5.Symmetric I/O Mode 3.6.2.3Symmetric I/O Mode3.6.5APIC Memory Mapping 3.6.4Floating Point Exception Interrupt3.6.8Multiple I/O APIC Configurations 3.6.7APIC Interval Timers3.6.6APIC Identification 3.7.1System-wideRESET 3.7 RESET Support3.7.3Processor-specificINIT 3.7.2System-wideINITVersion 3-153.8 System Initial State 3.9 Support for Fault-resilientBootingFigure 4-1.MP Configuration Data Structures 4 MP Configuration TableThe following two data structures are used Figure 4-2.MP Floating Pointer Structure 4.1MP Floating Pointer StructureTable 4-1.MP Floating Pointer Structure Fields Offset MultiProcessor SpecificationLength FieldFigure 4-3.MP Configuration Table Header 4.2MP Configuration Table Header1CH 10H ENTRY TYPE 4.3BaseMP Configuration Table Entries4.3.1Processor Entries Table 4-3. BaseMP Configuration TableEntry TypesFigure 4-4.Processor Entry Table 4-4.Processor Entry Fields MP Configuration Table Table 4-6.Feature Flags from CPUID InstructionFamily ModelFigure 4-5.Bus Entry Table 4-7.Bus Entry Fields 4.3.2 Bus EntriesTable 4-8.Bus Type String Values MP Configuration TableBus Type String Description4.3.4 I/O Interrupt Assignment Entries 4.3.3 I/O APIC EntriesI/O APIC Entry Table 4-9.I/O APIC Entry FieldsVersion Figure 4-7.I/O Interrupt Entry4-13 Table 4-10.I/O Interrupt Entry Fields Table 4-11.Interrupt Type Values 4.3.5Local Interrupt Assignment EntriesFigure 4-8.Local Interrupt Entry Table 4-12.Local Interrupt Entry Fields MultiProcessor SpecificationOffset in Length4.4Extended MP Configuration Table Entries Figure 4-9.System Address Space Entry 4.4.1System Address Space Mapping EntriesOffset MP Configuration TableLength FieldSince all device settings must fall within supported System Address Space mapping for a given bus in order to be usable by the operating system, buses that do not support dynamically configurable devices i.e., ISA, EISA should support all possible addresses to that bus Figure 4-11.Bus Hierarchy Descriptor Entry 4.4.2Bus Hierarchy Descriptor EntryOffset Table 4-15Bus Hierarchy Descriptor Entry FieldsLength Field4-23 VersionPREDEFINED RANGE LIST ADDRESS MODTable 4-17.Predefined Range Lists 5 Default Configurations Table 5-1.Default Configurations 5.1 Discrete APIC ConfigurationsVersion Default ConfigurationsSHADED AREAS MARK5.2 Integrated APIC Configurations SHADED AREAS VersionB,C EISA BUS SPECIFIC D PCI BUS SPECIFIC MARKMultiProcessor Specification 5.3.2Level-triggeredInterrupt Support 5.3.1EISA and IRQ13The 8259A INTR output signal is connected to the LINTIN0 of all local APICs, which makes INTR dynamically routable via software. NMI is connected to the LINTIN1 of all local APICs, which makes NMI dynamically routable via software A.1 BIOS Post Initialization A System BIOS Programming GuidelinesA.2 Controlling the Application Processors A.3 Programming the APIC for Virtual Wire ModeVersion System BIOS Programming GuidelinesA.4 Constructing the MP Configuration Table Version Page B.1 Operating System Boot-up B Operating System Programming GuidelinesB.3 Interrupt Mode Initialization and Handling Example B-1.Universal Start-upAlgorithm B.4 Application Processor StartupB.4.1 USINGINIT IPI B.5 APShutdown Handling B.4.2 USINGSTARTUP IPIB.7 Spurious APIC Interrupts B.6 Other IPI ApplicationsB.6.1 Handling Cache Flush B.6.2 Handling TLB InvalidationVersion B.8 Supporting Unequal ProcessorsPage Any NO answer indicates non-compliance C System Compliance ChecklistCondition Page D.1 Interrupt Routing with Multiple APICs D Multiple I/O APIC Multiple PCI Bus SystemsD.1.1 Variable Interrupt Routing D.1.2 Fixed Interrupt Routing Offset Multiple I/O APIC Multiple PCI Bus SystemsLength FieldPage Version E ErrataSIGNATURE Figure 4-9.System Address Space Entry 4.4.1 System Address Space Mapping EntriesENTRY TYPE space records must also be provided 4.4.2 Bus Hierarchy Descriptor EntryTable 4-15Bus Hierarchy Descriptor Entry Fields Figure 4-11.Bus Hierarchy Descriptor EntryGlossary Glossary-2 Order Number