Goals, Conceptual Overview | Intel MultiProcessor instruction

1 Introduction

The MultiProcessor Specification, hereafter known as the “MP specification,” defines an enhancement to the standard to which PC manufacturers design DOS-compatible systems. MP-capable operating systems will be able to run without special customization on multiprocessor systems that comply with this specification. End users who purchase a compliant multiprocessor system will be able to run their choice of operating systems.

The MP specification covers PC/AT-compatible MP platform designs based on Intel processor architectures and Advanced Programmable Interrupt Controller (APIC) architectures. The term “PC/AT-compatible” here refers to the software-visible components of the PC/AT, not to hardware features, such as the bus implementation, that are not visible to software. An implementation of this specification may incorporate one or more industry standard buses, such as ISA, EISA, MCA, PCI, or other OEM-specific buses.

1.1 Goals

The intent of this specification is to establish an MP Platform interface standard that extends the performance of the existing PC/AT platform beyond the traditional single processor limit, while maintaining 100% PC/AT binary compatibility.

The ultimate goal is to enable scalable, high-end workstations and enterprise server systems that provide computer users with superior price/performance and have the ability to execute all existing AT binaries, as well as MP-ready software packages on shrink-wrapped MP operating systems. Figure 1-1 shows that at the heart of the specification are the data structures that define the configuration of the MP system. The BIOS constructs the MP configuration data structures, presenting the hardware in a known format to the standard device drivers or to the hardware abstraction layer of the operating system. The specification details default hardware configurations, and, for added flexibility, outlines extensions to the standard BIOS.

	OPERATING SYSTEM
	DRIVER/
	HARDWARE
	ABSTRACTION LAYER
MP BIOS	MP
	MP
	CONFIGURATION
	DATA
	STRUCTURES
	HARDWARE

Figure 1-1. Conceptual Overview

Version 1.4

1-1

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Intel MultiProcessor manual Goals, Conceptual Overview

Contents

MultiProcessor Specification Copyright 1993-1997. Intel Corporation, All Rights Reserved Revision Revision History Date Revision HistoryPage Table of Contents Contents MP Configuration TableDefault Configurations Appendix E Errata Glossary Appendix a System Bios Programming GuidelinesAppendix B Operating System Programming Guidelines Tables Figures Examples Page Conceptual Overview Goals Scope Features of the SpecificationMultiProcessor Specification Introduction Target AudienceOrganization of This Document Document Organization For More Information Conventions Used in This Document System Overview System Processors Hardware Overview System Overview Advanced Programmable Interrupt Controller 4 I/O Expansion Bus System Memory Operating System Overview Bios OverviewPage System Memory Configuration Hardware Specification System Memory Address Map System Memory Cacheability and Shareability Memory Cacheability Map Hardware Specification Locking External Cache Subsystem Apic Architecture Posted Memory WriteMultiprocessor Interrupt Control Apic Versions Interrupt Modes PIC Mode PIC Mode Virtual Wire Mode via Local Apic Virtual Wire Mode Virtual Wire Mode via I/O Apic Symmetric I/O Mode Symmetric I/O Mode Apic Memory Mapping Assignment of System Interrupts to the Apic Local UnitFloating Point Exception Interrupt Apic Identification Apic Interval Timers System-wide Reset Reset Support Processor-specific Init System-wide Init System Initial State Support for Fault-resilient Booting MP Configuration Table MultiProcessor Specification Offset Length Field Bytesbits in bits Description MP Configuration TableMP Floating Pointer Structure Information Bytes MP FeatureOffset Length Field Bytesbits Bits Description Information Byte MP Configuration Table Header MP Configuration Table Header Offset Length Field Bytes Bits Description Base MP Configuration Table EntriesMP Configuration Table Header Fields Apic Base MP Configuration Table Entry TypesProcessor Entries Length Entry Description Entry Type Code Bytes Comments Processor Entry Fields Bit Name Description Comments Feature Flags from Cpuid InstructionIntel486 and Pentium Processor Signatures Family Model Stepping a Description String Bus EntriesBUS ID BUS Type Bus Type String Description Bus Type String Values I/O Apic Entry Fields 3 I/O Apic Entries4 I/O Interrupt Assignment Entries Apic Entry I/O Interrupt Entry 10. I/O Interrupt Entry Fields Interrupt Type Description Comments Local Interrupt Assignment Entries11. Interrupt Type Values LINTIN# 12. Local Interrupt Entry FieldsDestination Local Apic ID Destination Local Apic Extended MP Configuration Table Entries System Address Space Mapping Entries 14. System Address Space Mapping Entry Fields 10. Example System with Multiple Bus Types and Bridge Types Bus Hierarchy Descriptor Entry Compatibility Bus Address Space Modifier Entry 12. Compatibility Bus Address Space Modifier Entry 16. Compatibility Bus Address Space Modifier Entry Fields Default Configurations Config Code CPUs Type Variant Schematic Discrete Apic ConfigurationsDefault Configurations Default Number Bus Default Configurations Default Configuration for Discrete Apic Integrated Apic Configurations Default Configuration for Integrated Apic First I/O Default Configuration Interrupt AssignmentsConfig INTINx Comments Assignment of I/O Interrupts to the Apic I/O Unit Level-triggered Interrupt Support All Local APICs Config LINTINx CommentsAssignment of System Interrupts to the Apic Local Unit Eisa and IRQ13 MultiProcessor Specification Bios Post Initialization System Bios Programming Guidelines Controlling the Application Processors Programming the Apic for Virtual Wire Mode System Bios Programming Guidelines Example A-1. Programming Local Apic for Virtual Wire Mode NMI Constructing the MP Configuration Table System Bios Programming Guidelines Page Operating System Programming Guidelines Operating System Boot-up Interrupt Mode Initialization and Handling Operating System Booting and Self-configuration Operating System Programming Guidelines Application Processor Startup Using Init IPI AP Shutdown Handling Using Startup IPI Handling TLB Invalidation Other IPI ApplicationsSpurious Apic Interrupts Handling Cache Flush Supporting Unequal Processors Page System Compliance Checklist Page Variable Interrupt Routing Interrupt Routing with Multiple APICs Fixed Interrupt Routing INTD# Bus Entries in Systems with More Than One PCI BusI/O Interrupt Assignment Entries for PCI Devices Multiple I/O Apic Multiple PCI Bus SystemsPage Errata 126 System Address Space Entry System Address Space Mapping Entries Address Base 14. System Address Space Mapping Entry FieldsEntry Length Address Type Space records must also be provided Bus Hierarchy Descriptor Entry Parent BUS BUS Informationsd Glossary Glossary-2 Order Number