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Intel MultiProcessor manual

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The 8259A INTR output signal is connected to the LINTIN0 of all local APICs, which makes INTR dynamically routable via software. NMI is connected to the LINTIN1 of all local APICs, which makes NMI dynamically routable via software.

MultiProcessor Specification

The 8259A INTR output signal is connected to the LINTIN0 of all local APICs, which makes INTR dynamically routable via software. NMI is connected to the LINTIN1 of all local APICs, which makes NMI dynamically routable via software.

In PIC-Mode configurations, the NMI signal is delivered to the local interrupt input 1 (LINTIN1) of all local APICs and the input of a 2-to-1 MUX. When the system is operated in PIC Mode, the NMI is sent to the BSP directly via the MUX. The BIOS and the operating system must leave the LINTIN1 of all local APICs disabled to ensure that the BSP is the only processor that receives the NMI.

In PIC-Mode configurations, the 8259 INTR signal also follows the same convention, connecting to the local interrupt line 0 (LINTIN0) of all local APICs and the input of the second 2-to-1 MUX. When the system is operated in PIC Mode, the 8259 INTR is sent to the BSP directly via the MUX. The BIOS and the operating system must leave the LINTIN0 of all local APICs disabled to ensure that the BSP is the only processor that receives the 8259 INTR signal.

When the system is operated in Symmetric I/O Mode, the operating system may enable the LINTIN0 and LINTIN1 of any or all local APICs as necessary.

5-8	Version 1.4

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Intel MultiProcessor manual

Contents

MultiProcessor Specification VersionIntel Corporation Literature Center P.O. Box Revision History RevisionRevision History DatePage Table of Contents Chapter 3 Hardware SpecificationChapter 1 Introduction Chapter 2 System OverviewChapter 4 MP Configuration Table Chapter 5 Default ConfigurationsAppendix E Errata Glossary Appendix A System BIOS Programming GuidelinesAppendix C System Compliance Checklist Figures TablesExamples Page 1 Introduction 1.1 Goals1.2 Features of the Specification 1.3ScopeIS EXPECTED TO REMAIN CONSTANT 1.4 Target Audience1.5Organization of This Document IN THE RESERVED FIELDS 1.6 Conventions Used in This Document1.7 For More Information 2 System Overview Version2.1 Hardware Overview 2.1.1System ProcessorsFigure 2-2.APIC Configuration 2.1.2Advanced Programmable Interrupt Controller2.1.3System Memory 2.1.4I/O Expansion Bus2.2 BIOS Overview 2.3 Operating System OverviewPage 3 Hardware Specification 3.1 System Memory Configuration3.2 System Memory Cacheability and Shareability Figure 3-1.System Memory Address MapHardware Specification Table 3-1.Memory Cacheability MapAddresses Shared by All3.3 External Cache Subsystem 3.4Locking3.6.1APIC Architecture 3.5 Posted Memory Write3.6 Multiprocessor Interrupt Control 3.6.2Interrupt Modes 3.6.2.1PIC Mode VersionFigure 3-2.PIC Mode 3.6.2.2Virtual Wire Mode Figure 3-3.Virtual Wire Mode via Local APICFigure 3-4.Virtual Wire Mode via I/O APIC 3-103.6.2.3Symmetric I/O Mode Figure 3-5.Symmetric I/O Mode3.6.4Floating Point Exception Interrupt 3.6.5APIC Memory Mapping3.6.6APIC Identification 3.6.7APIC Interval Timers3.6.8Multiple I/O APIC Configurations 3.7 RESET Support 3.7.1System-wideRESET3.7.2System-wideINIT 3.7.3Processor-specificINITVersion 3-153.9 Support for Fault-resilientBooting 3.8 System Initial State4 MP Configuration Table Figure 4-1.MP Configuration Data StructuresThe following two data structures are used Table 4-1.MP Floating Pointer Structure Fields 4.1MP Floating Pointer StructureFigure 4-2.MP Floating Pointer Structure MultiProcessor Specification OffsetLength Field1CH 10H 4.2MP Configuration Table HeaderFigure 4-3.MP Configuration Table Header 4.3BaseMP Configuration Table Entries ENTRY TYPEFigure 4-4.Processor Entry Table 4-3. BaseMP Configuration TableEntry Types4.3.1Processor Entries Table 4-4.Processor Entry Fields Table 4-6.Feature Flags from CPUID Instruction MP Configuration TableFamily Model4.3.2 Bus Entries Figure 4-5.Bus Entry Table 4-7.Bus Entry FieldsMP Configuration Table Table 4-8.Bus Type String ValuesBus Type String Description4.3.3 I/O APIC Entries 4.3.4 I/O Interrupt Assignment EntriesI/O APIC Entry Table 4-9.I/O APIC Entry Fields4-13 Figure 4-7.I/O Interrupt EntryVersion Table 4-10.I/O Interrupt Entry Fields Figure 4-8.Local Interrupt Entry 4.3.5Local Interrupt Assignment EntriesTable 4-11.Interrupt Type Values MultiProcessor Specification Table 4-12.Local Interrupt Entry FieldsOffset in Length4.4Extended MP Configuration Table Entries 4.4.1System Address Space Mapping Entries Figure 4-9.System Address Space EntryMP Configuration Table OffsetLength FieldSince all device settings must fall within supported System Address Space mapping for a given bus in order to be usable by the operating system, buses that do not support dynamically configurable devices i.e., ISA, EISA should support all possible addresses to that bus 4.4.2Bus Hierarchy Descriptor Entry Figure 4-11.Bus Hierarchy Descriptor EntryTable 4-15Bus Hierarchy Descriptor Entry Fields OffsetLength FieldVersion 4-23PREDEFINED RANGE LIST ADDRESS MODTable 4-17.Predefined Range Lists 5 Default Configurations 5.1 Discrete APIC Configurations Table 5-1.Default ConfigurationsDefault Configurations VersionSHADED AREAS MARK5.2 Integrated APIC Configurations Version SHADED AREASB,C EISA BUS SPECIFIC D PCI BUS SPECIFIC MARKMultiProcessor Specification 5.3.1EISA and IRQ13 5.3.2Level-triggeredInterrupt SupportThe 8259A INTR output signal is connected to the LINTIN0 of all local APICs, which makes INTR dynamically routable via software. NMI is connected to the LINTIN1 of all local APICs, which makes NMI dynamically routable via software A System BIOS Programming Guidelines A.1 BIOS Post InitializationA.3 Programming the APIC for Virtual Wire Mode A.2 Controlling the Application ProcessorsSystem BIOS Programming Guidelines VersionA.4 Constructing the MP Configuration Table Version Page B Operating System Programming Guidelines B.1 Operating System Boot-upB.3 Interrupt Mode Initialization and Handling B.4 Application Processor Startup Example B-1.Universal Start-upAlgorithmB.4.1 USINGINIT IPI B.4.2 USINGSTARTUP IPI B.5 APShutdown HandlingB.6 Other IPI Applications B.7 Spurious APIC InterruptsB.6.1 Handling Cache Flush B.6.2 Handling TLB InvalidationB.8 Supporting Unequal Processors VersionPage Condition C System Compliance ChecklistAny NO answer indicates non-compliance Page D.1.1 Variable Interrupt Routing D Multiple I/O APIC Multiple PCI Bus SystemsD.1 Interrupt Routing with Multiple APICs D.1.2 Fixed Interrupt Routing Multiple I/O APIC Multiple PCI Bus Systems OffsetLength FieldPage E Errata VersionSIGNATURE 4.4.1 System Address Space Mapping Entries Figure 4-9.System Address Space EntryENTRY TYPE 4.4.2 Bus Hierarchy Descriptor Entry space records must also be providedFigure 4-11.Bus Hierarchy Descriptor Entry Table 4-15Bus Hierarchy Descriptor Entry FieldsGlossary Glossary-2 Order Number