
MP Configuration Table
Table 4-5.  Intel486 and Pentium Processor Signatures
| Family | Model | Steppinga | Description | 
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| 0000 | 0000 | 0000 | Not a valid CPU signature. | 
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 | 
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| 0100 | 0000 and 0001 | xxxx | Intel486 DX Processor | 
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 | 
 | 
| 0100 | 0010 | xxxx | Intel486 SX Processor | 
| 
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| 0100 | 0011 | xxxx | Intel487 Processor | 
| 
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| 0100 | 0011 | xxxx | IntelDX2™ Processor | 
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| 0100 | 0100 | xxxx | Intel486 SL Processor | 
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| 0100 | 0101 | xxxx | IntelSX2™ Processor | 
| 
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| 0100 | 1000 | xxxx | IntelDX4™ Processor | 
| 
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| 0101 | 0001 | xxxx | Pentium Processors (510\60, 567\66) | 
| 
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| 0101 | 0010 | xxxx | Pentium Processors (735\90, 815\100) | 
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 | ||
| 
 | Values not shown are reserved for future processors. | ||
| 
 | Refer to the documentation of each new processor for its family and model values. | ||
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 | 
| 1111 | 1111 | 1111 | Not a valid CPU signature. Indicates a processor that is not | 
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 | an Intel  | 
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 | 
 | controller, for example) | 
a Intel releases information about stepping numbers as needed.
Table 4-6.  Feature Flags from CPUID Instruction
| Bit | Name | Description | Comments | 
| 0 | FPU | The processor contains an FPU that supports the Intel387 | |
| 
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 | Point Unit | processor floating point instruction set. | 
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| 
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 | Reserved. | |
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| 7 | MCE | Machine Check | Exception 18 is defined for machine checks, including CR4.MCE for | 
| 
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 | Exception | controlling the feature. This feature does not define the model- | 
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 | specific implementations of  | 
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 | and processor shutdowns.  | 
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 | have to depend on processor version to do  | 
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 | processing of the exception or test for the presence of the standard | 
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 | |
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| 8 | CX8 | CMPXCHG8B | The 8 byte (64 bits)  | 
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 | Instruction | (implicitly locked and atomic). Introduced by the Pentium | 
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 | processor. | 
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| 9 | APIC | Indicates that an integrated APIC is present and hardware enabled. | |
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 | (Software disabling does not affect this bit.) | 
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 | Reserved. | |
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| Version 1.4 | 
