Virtual Wire Mode | Intel MultiProcessor guide

Hardware Specification

3.6.2.2Virtual Wire Mode

Virtual Wire Mode provides a uniprocessor hardware environment capable of booting and running all DOS shrink-wrapped software.

In Virtual Wire Mode, as shown in Figure 3-3, the 8259A-equivalent PIC fields all interrupts, and the local APIC of the BSP becomes a virtual wire, which delivers interrupts from the PIC to the BSP via the local APIC’s local interrupt 0 (LINTIN0). The LINTIN0 pin of the local APIC is programmed as ExtINT, specifying to the APIC that the PIC is to serve as an external interrupt controller. Whenever the local APIC finds that a particular interrupt is of type ExtINT, it asserts the ExtINTA transaction along with the PINT interrupt to the processor. In this case, the I/O APIC is not used.

BSP		AP1		AP2
CPU 1		CPU 2		CPU 3

	NMI	INTR		NMI INTR		NMI	INTR
		LOCAL		LOCAL			LOCAL
REG.		APIC		APIC			APIC
REG.		1		2				3
MARK	LINTIN0		LINTIN1	LINTIN0	LINTIN1	LINTIN0		LINTIN1
	LINTIN0		LINTIN1	LINTIN0	LINTIN1	LINTIN0		LINTIN1
LINTIN1
LINTIN0
RESET
ICC BUS
NMI
				8259A-	INTR
				EQUIVALENT
				PICS
INTERRUPT INPUTS								I/O
INTERRUPT INPUTS								APIC
								APIC

SHADED AREAS INDICATE UNUSED CIRCUITS. DOTTED LINE SHOWS INTERRUPT PATH.

Figure 3-3. Virtual Wire Mode via Local APIC

Version 1.4

3-9

Image 29

Intel MultiProcessor manual Virtual Wire Mode via Local Apic

Contents

MultiProcessor Specification Copyright 1993-1997. Intel Corporation, All Rights Reserved Revision Revision History Date Revision HistoryPage Table of Contents Contents MP Configuration TableDefault Configurations Appendix E Errata Glossary Appendix a System Bios Programming GuidelinesAppendix B Operating System Programming Guidelines Tables Figures Examples Page Conceptual Overview Goals Scope Features of the SpecificationMultiProcessor Specification Organization of This Document Target AudienceDocument Organization Introduction For More Information Conventions Used in This Document System Overview System Processors Hardware Overview System Overview Advanced Programmable Interrupt Controller 4 I/O Expansion Bus System Memory Operating System Overview Bios OverviewPage System Memory Configuration Hardware Specification System Memory Address Map System Memory Cacheability and Shareability Memory Cacheability Map Hardware Specification Locking External Cache Subsystem Apic Architecture Posted Memory WriteMultiprocessor Interrupt Control Apic Versions Interrupt Modes PIC Mode PIC Mode Virtual Wire Mode via Local Apic Virtual Wire Mode Virtual Wire Mode via I/O Apic Symmetric I/O Mode Symmetric I/O Mode Apic Memory Mapping Assignment of System Interrupts to the Apic Local UnitFloating Point Exception Interrupt Apic Identification Apic Interval Timers System-wide Reset Reset Support Processor-specific Init System-wide Init System Initial State Support for Fault-resilient Booting MP Configuration Table MultiProcessor Specification Offset Length Field Bytesbits in bits Description MP Configuration TableMP Floating Pointer Structure Offset Length Field Bytesbits Bits Description MP FeatureInformation Byte Information Bytes MP Configuration Table Header MP Configuration Table Header Offset Length Field Bytes Bits Description Base MP Configuration Table EntriesMP Configuration Table Header Fields Processor Entries Base MP Configuration Table Entry TypesLength Entry Description Entry Type Code Bytes Comments Apic Processor Entry Fields Intel486 and Pentium Processor Signatures Feature Flags from Cpuid InstructionFamily Model Stepping a Description Bit Name Description Comments BUS ID Bus EntriesBUS Type String Bus Type String Description Bus Type String Values 4 I/O Interrupt Assignment Entries 3 I/O Apic EntriesApic Entry I/O Apic Entry Fields I/O Interrupt Entry 10. I/O Interrupt Entry Fields Interrupt Type Description Comments Local Interrupt Assignment Entries11. Interrupt Type Values Destination Local Apic ID 12. Local Interrupt Entry FieldsDestination Local Apic LINTIN# Extended MP Configuration Table Entries System Address Space Mapping Entries 14. System Address Space Mapping Entry Fields 10. Example System with Multiple Bus Types and Bridge Types Bus Hierarchy Descriptor Entry Compatibility Bus Address Space Modifier Entry 12. Compatibility Bus Address Space Modifier Entry 16. Compatibility Bus Address Space Modifier Entry Fields Default Configurations Default Configurations Discrete Apic ConfigurationsDefault Number Bus Config Code CPUs Type Variant Schematic Default Configurations Default Configuration for Discrete Apic Integrated Apic Configurations Default Configuration for Integrated Apic Config INTINx Comments Default Configuration Interrupt AssignmentsAssignment of I/O Interrupts to the Apic I/O Unit First I/O Assignment of System Interrupts to the Apic Local Unit All Local APICs Config LINTINx CommentsEisa and IRQ13 Level-triggered Interrupt Support MultiProcessor Specification Bios Post Initialization System Bios Programming Guidelines Controlling the Application Processors Programming the Apic for Virtual Wire Mode System Bios Programming Guidelines Example A-1. Programming Local Apic for Virtual Wire Mode NMI Constructing the MP Configuration Table System Bios Programming Guidelines Page Operating System Programming Guidelines Operating System Boot-up Interrupt Mode Initialization and Handling Operating System Booting and Self-configuration Operating System Programming Guidelines Application Processor Startup Using Init IPI AP Shutdown Handling Using Startup IPI Spurious Apic Interrupts Other IPI ApplicationsHandling Cache Flush Handling TLB Invalidation Supporting Unequal Processors Page System Compliance Checklist Page Variable Interrupt Routing Interrupt Routing with Multiple APICs Fixed Interrupt Routing I/O Interrupt Assignment Entries for PCI Devices Bus Entries in Systems with More Than One PCI BusMultiple I/O Apic Multiple PCI Bus Systems INTD#Page Errata 126 System Address Space Entry System Address Space Mapping Entries Entry Length 14. System Address Space Mapping Entry FieldsAddress Type Address Base Space records must also be provided Bus Hierarchy Descriptor Entry Parent BUS BUS Informationsd Glossary Glossary-2 Order Number