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Intel MultiProcessor manual 3.6.2.2Virtual Wire Mode, 3.Virtual Wire Mode via Local APIC

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3.6.2.2Virtual Wire Mode

Hardware Specification

3.6.2.2Virtual Wire Mode

Virtual Wire Mode provides a uniprocessor hardware environment capable of booting and running all DOS shrink-wrapped software.

In Virtual Wire Mode, as shown in Figure 3-3, the 8259A-equivalent PIC fields all interrupts, and the local APIC of the BSP becomes a virtual wire, which delivers interrupts from the PIC to the BSP via the local APIC’s local interrupt 0 (LINTIN0). The LINTIN0 pin of the local APIC is programmed as ExtINT, specifying to the APIC that the PIC is to serve as an external interrupt controller. Whenever the local APIC finds that a particular interrupt is of type ExtINT, it asserts the ExtINTA transaction along with the PINT interrupt to the processor. In this case, the I/O APIC is not used.

BSP		AP1		AP2
CPU 1		CPU 2		CPU 3

	NMI	INTR		NMI INTR		NMI	INTR
		LOCAL		LOCAL			LOCAL
REG.		APIC		APIC			APIC
REG.		1		2				3
MARK	LINTIN0		LINTIN1	LINTIN0	LINTIN1	LINTIN0		LINTIN1
	LINTIN0		LINTIN1	LINTIN0	LINTIN1	LINTIN0		LINTIN1
LINTIN1
LINTIN0
RESET
ICC BUS
NMI
				8259A-	INTR
				EQUIVALENT
				PICS
INTERRUPT INPUTS								I/O
INTERRUPT INPUTS								APIC
								APIC

SHADED AREAS INDICATE UNUSED CIRCUITS. DOTTED LINE SHOWS INTERRUPT PATH.

Figure 3-3. Virtual Wire Mode via Local APIC

Version 1.4

3-9

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Intel MultiProcessor manual 3.6.2.2Virtual Wire Mode, 3.Virtual Wire Mode via Local APIC

Contents

Version MultiProcessor SpecificationIntel Corporation Literature Center P.O. Box Revision Revision HistoryRevision History DatePage Chapter 3 Hardware Specification Table of ContentsChapter 1 Introduction Chapter 2 System OverviewChapter 5 Default Configurations Chapter 4 MP Configuration TableAppendix E Errata Glossary Appendix A System BIOS Programming GuidelinesAppendix C System Compliance Checklist Tables FiguresExamples Page 1.1 Goals 1 Introduction1.3Scope 1.2 Features of the SpecificationIS EXPECTED TO REMAIN CONSTANT 1.4 Target Audience1.5Organization of This Document IN THE RESERVED FIELDS 1.6 Conventions Used in This Document1.7 For More Information Version 2 System Overview2.1.1System Processors 2.1 Hardware Overview2.1.2Advanced Programmable Interrupt Controller Figure 2-2.APIC Configuration2.1.4I/O Expansion Bus 2.1.3System Memory2.3 Operating System Overview 2.2 BIOS OverviewPage 3.1 System Memory Configuration 3 Hardware SpecificationFigure 3-1.System Memory Address Map 3.2 System Memory Cacheability and ShareabilityTable 3-1.Memory Cacheability Map Hardware SpecificationAddresses Shared by All3.4Locking 3.3 External Cache Subsystem3.6.1APIC Architecture 3.5 Posted Memory Write3.6 Multiprocessor Interrupt Control 3.6.2Interrupt Modes Version 3.6.2.1PIC ModeFigure 3-2.PIC Mode Figure 3-3.Virtual Wire Mode via Local APIC 3.6.2.2Virtual Wire Mode3-10 Figure 3-4.Virtual Wire Mode via I/O APICFigure 3-5.Symmetric I/O Mode 3.6.2.3Symmetric I/O Mode3.6.5APIC Memory Mapping 3.6.4Floating Point Exception Interrupt3.6.6APIC Identification 3.6.7APIC Interval Timers3.6.8Multiple I/O APIC Configurations 3.7.1System-wideRESET 3.7 RESET Support3.7.3Processor-specificINIT 3.7.2System-wideINITVersion 3-153.8 System Initial State 3.9 Support for Fault-resilientBootingFigure 4-1.MP Configuration Data Structures 4 MP Configuration TableThe following two data structures are used Table 4-1.MP Floating Pointer Structure Fields 4.1MP Floating Pointer StructureFigure 4-2.MP Floating Pointer Structure Offset MultiProcessor SpecificationLength Field1CH 10H 4.2MP Configuration Table HeaderFigure 4-3.MP Configuration Table Header ENTRY TYPE 4.3BaseMP Configuration Table EntriesFigure 4-4.Processor Entry Table 4-3. BaseMP Configuration TableEntry Types4.3.1Processor Entries Table 4-4.Processor Entry Fields MP Configuration Table Table 4-6.Feature Flags from CPUID InstructionFamily ModelFigure 4-5.Bus Entry Table 4-7.Bus Entry Fields 4.3.2 Bus EntriesTable 4-8.Bus Type String Values MP Configuration TableBus Type String Description4.3.4 I/O Interrupt Assignment Entries 4.3.3 I/O APIC EntriesI/O APIC Entry Table 4-9.I/O APIC Entry Fields4-13 Figure 4-7.I/O Interrupt EntryVersion Table 4-10.I/O Interrupt Entry Fields Figure 4-8.Local Interrupt Entry 4.3.5Local Interrupt Assignment EntriesTable 4-11.Interrupt Type Values Table 4-12.Local Interrupt Entry Fields MultiProcessor SpecificationOffset in Length4.4Extended MP Configuration Table Entries Figure 4-9.System Address Space Entry 4.4.1System Address Space Mapping EntriesOffset MP Configuration TableLength FieldSince all device settings must fall within supported System Address Space mapping for a given bus in order to be usable by the operating system, buses that do not support dynamically configurable devices i.e., ISA, EISA should support all possible addresses to that bus Figure 4-11.Bus Hierarchy Descriptor Entry 4.4.2Bus Hierarchy Descriptor EntryOffset Table 4-15Bus Hierarchy Descriptor Entry FieldsLength Field4-23 VersionPREDEFINED RANGE LIST ADDRESS MODTable 4-17.Predefined Range Lists 5 Default Configurations Table 5-1.Default Configurations 5.1 Discrete APIC ConfigurationsVersion Default ConfigurationsSHADED AREAS MARK5.2 Integrated APIC Configurations SHADED AREAS VersionB,C EISA BUS SPECIFIC D PCI BUS SPECIFIC MARKMultiProcessor Specification 5.3.2Level-triggeredInterrupt Support 5.3.1EISA and IRQ13The 8259A INTR output signal is connected to the LINTIN0 of all local APICs, which makes INTR dynamically routable via software. NMI is connected to the LINTIN1 of all local APICs, which makes NMI dynamically routable via software A.1 BIOS Post Initialization A System BIOS Programming GuidelinesA.2 Controlling the Application Processors A.3 Programming the APIC for Virtual Wire ModeVersion System BIOS Programming GuidelinesA.4 Constructing the MP Configuration Table Version Page B.1 Operating System Boot-up B Operating System Programming GuidelinesB.3 Interrupt Mode Initialization and Handling Example B-1.Universal Start-upAlgorithm B.4 Application Processor StartupB.4.1 USINGINIT IPI B.5 APShutdown Handling B.4.2 USINGSTARTUP IPIB.7 Spurious APIC Interrupts B.6 Other IPI ApplicationsB.6.1 Handling Cache Flush B.6.2 Handling TLB InvalidationVersion B.8 Supporting Unequal ProcessorsPage Condition C System Compliance ChecklistAny NO answer indicates non-compliance Page D.1.1 Variable Interrupt Routing D Multiple I/O APIC Multiple PCI Bus SystemsD.1 Interrupt Routing with Multiple APICs D.1.2 Fixed Interrupt Routing Offset Multiple I/O APIC Multiple PCI Bus SystemsLength FieldPage Version E ErrataSIGNATURE Figure 4-9.System Address Space Entry 4.4.1 System Address Space Mapping EntriesENTRY TYPE space records must also be provided 4.4.2 Bus Hierarchy Descriptor EntryTable 4-15Bus Hierarchy Descriptor Entry Fields Figure 4-11.Bus Hierarchy Descriptor EntryGlossary Glossary-2 Order Number