Intel MultiProcessor manual Bus Hierarchy Descriptor Entry

MP Configuration Table

4.4.2Bus Hierarchy Descriptor Entry

If present, Bus Hierarchy Descriptor entries define how I/O buses are connected relative to each other in a system with more than one I/O bus. Bus Hierarchy Descriptors are used to supplement System Address Mapping entries to describe how addresses propagate to particular buses in systems where address decoding cannot be completely described by System Address Space Mapping entries alone. Entries of this type are required for each bus that is connected to the system hierarchically below another I/O bus. For example, given the system described in Figure 4-10, bus hierarchy entries are required for the EISA bus and the PCI BUS 2 since both have parent buses that are themselves I/O buses.

The Bus Hierarchy entry provides information about where in a hierarchical connection scheme a given bus is connected and the type of address decoding performed for that bus. Figure 4-11 shows the format of each entry, and Table 4-15 explains each field. See also Appendix E, for more information.

3 1 2 8 2 7 24 2 3 2 0 1 9 1 6 1 5 1 2 1 1 8 7 4 3 0

			RESERVED						PARENT BUS
	BUS INFO	S	BUS ID		ENTRY LENG TH				ENTRY TYPE
									129
	RESERVED	D
3 1	2 8 2 7	24 2 3	2 0 1 9	1 6	1 5	1 2 1 1	8	7	4	3	0

04H

00H

Figure 4-11. Bus Hierarchy Descriptor Entry

Version 1.4 4-21