PIC Mode | Intel MultiProcessor specification

Hardware Specification

The first two interrupt modes, PIC Mode and Virtual Wire Mode, provide PC/AT-compatibility. At least one of these modes must be implemented in systems that comply with the MP specification. In these modes, full DOS compatibility with the uniprocessor PC/AT is provided by using the APICs in conjunction with standard 8259A-equivalent programmable interrupt controllers (PICs).

The third mode, Symmetric I/O Mode, must be implemented in addition to either PIC Mode or Virtual Wire Mode. An MP operating system is booted under either one of the two PC/AT- compatible modes. Later the operating system switches to Symmetric I/O Mode as it enters multiprocessor mode.

The interrupt modes are implemented by a combination of hardware and software. The hardware and programming specifications for each of these modes are further defined in the following subsections. BIOS programmers should refer to Appendix A, which includes information about programming the APIC for Virtual Wire Mode. Operating system programmers should refer to Appendix B, which provides more information about initializing the APIC for Symmetric I/O Mode.

3.6.2.1PIC Mode

PIC Mode is software compatible with the PC/AT because it actually employs the same hardware interrupt configuration. As Figure 3-2 illustrates, the hardware for PIC Mode bypasses the APIC components by using an interrupt mode configuration register (IMCR). This register controls whether the interrupt signals that reach the BSP come from the master PIC or from the local APIC. Before entering Symmetric I/O Mode, either the BIOS or the operating system must switch out of PIC Mode by changing the IMCR.

Version 1.4

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Intel MultiProcessor manual PIC Mode

Contents

MultiProcessor Specification Copyright 1993-1997. Intel Corporation, All Rights Reserved Revision Revision History Date Revision HistoryPage Table of Contents MP Configuration Table Default ConfigurationsContents Appendix a System Bios Programming Guidelines Appendix B Operating System Programming GuidelinesAppendix E Errata Glossary Tables Figures Examples Page Conceptual Overview Goals Features of the Specification MultiProcessor SpecificationScope Introduction Target AudienceOrganization of This Document Document Organization For More Information Conventions Used in This Document System Overview System Processors Hardware Overview System Overview Advanced Programmable Interrupt Controller 4 I/O Expansion Bus System Memory Operating System Overview Bios OverviewPage System Memory Configuration Hardware Specification System Memory Address Map System Memory Cacheability and Shareability Memory Cacheability Map Hardware Specification Locking External Cache Subsystem Posted Memory Write Multiprocessor Interrupt ControlApic Architecture Apic Versions Interrupt Modes PIC Mode PIC Mode Virtual Wire Mode via Local Apic Virtual Wire Mode Virtual Wire Mode via I/O Apic Symmetric I/O Mode Symmetric I/O Mode Assignment of System Interrupts to the Apic Local Unit Floating Point Exception InterruptApic Memory Mapping Apic Identification Apic Interval Timers System-wide Reset Reset Support Processor-specific Init System-wide Init System Initial State Support for Fault-resilient Booting MP Configuration Table MultiProcessor Specification MP Configuration Table MP Floating Pointer StructureOffset Length Field Bytesbits in bits Description Information Bytes MP FeatureOffset Length Field Bytesbits Bits Description Information Byte MP Configuration Table Header MP Configuration Table Header Base MP Configuration Table Entries MP Configuration Table Header FieldsOffset Length Field Bytes Bits Description Apic Base MP Configuration Table Entry TypesProcessor Entries Length Entry Description Entry Type Code Bytes Comments Processor Entry Fields Bit Name Description Comments Feature Flags from Cpuid InstructionIntel486 and Pentium Processor Signatures Family Model Stepping a Description String Bus EntriesBUS ID BUS Type Bus Type String Description Bus Type String Values I/O Apic Entry Fields 3 I/O Apic Entries4 I/O Interrupt Assignment Entries Apic Entry I/O Interrupt Entry 10. I/O Interrupt Entry Fields Local Interrupt Assignment Entries 11. Interrupt Type ValuesInterrupt Type Description Comments LINTIN# 12. Local Interrupt Entry FieldsDestination Local Apic ID Destination Local Apic Extended MP Configuration Table Entries System Address Space Mapping Entries 14. System Address Space Mapping Entry Fields 10. Example System with Multiple Bus Types and Bridge Types Bus Hierarchy Descriptor Entry Compatibility Bus Address Space Modifier Entry 12. Compatibility Bus Address Space Modifier Entry 16. Compatibility Bus Address Space Modifier Entry Fields Default Configurations Config Code CPUs Type Variant Schematic Discrete Apic ConfigurationsDefault Configurations Default Number Bus Default Configurations Default Configuration for Discrete Apic Integrated Apic Configurations Default Configuration for Integrated Apic First I/O Default Configuration Interrupt AssignmentsConfig INTINx Comments Assignment of I/O Interrupts to the Apic I/O Unit Level-triggered Interrupt Support All Local APICs Config LINTINx CommentsAssignment of System Interrupts to the Apic Local Unit Eisa and IRQ13 MultiProcessor Specification Bios Post Initialization System Bios Programming Guidelines Controlling the Application Processors Programming the Apic for Virtual Wire Mode System Bios Programming Guidelines Example A-1. Programming Local Apic for Virtual Wire Mode NMI Constructing the MP Configuration Table System Bios Programming Guidelines Page Operating System Programming Guidelines Operating System Boot-up Interrupt Mode Initialization and Handling Operating System Booting and Self-configuration Operating System Programming Guidelines Application Processor Startup Using Init IPI AP Shutdown Handling Using Startup IPI Handling TLB Invalidation Other IPI ApplicationsSpurious Apic Interrupts Handling Cache Flush Supporting Unequal Processors Page System Compliance Checklist Page Variable Interrupt Routing Interrupt Routing with Multiple APICs Fixed Interrupt Routing INTD# Bus Entries in Systems with More Than One PCI BusI/O Interrupt Assignment Entries for PCI Devices Multiple I/O Apic Multiple PCI Bus SystemsPage Errata 126 System Address Space Entry System Address Space Mapping Entries Address Base 14. System Address Space Mapping Entry FieldsEntry Length Address Type Space records must also be provided Bus Hierarchy Descriptor Entry Parent BUS BUS Informationsd Glossary Glossary-2 Order Number