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Intel MultiProcessor manual 3.6.2.1PIC Mode, Version

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3.6.2.1PIC Mode

Hardware Specification

The first two interrupt modes, PIC Mode and Virtual Wire Mode, provide PC/AT-compatibility. At least one of these modes must be implemented in systems that comply with the MP specification. In these modes, full DOS compatibility with the uniprocessor PC/AT is provided by using the APICs in conjunction with standard 8259A-equivalent programmable interrupt controllers (PICs).

The third mode, Symmetric I/O Mode, must be implemented in addition to either PIC Mode or Virtual Wire Mode. An MP operating system is booted under either one of the two PC/AT- compatible modes. Later the operating system switches to Symmetric I/O Mode as it enters multiprocessor mode.

The interrupt modes are implemented by a combination of hardware and software. The hardware and programming specifications for each of these modes are further defined in the following subsections. BIOS programmers should refer to Appendix A, which includes information about programming the APIC for Virtual Wire Mode. Operating system programmers should refer to Appendix B, which provides more information about initializing the APIC for Symmetric I/O Mode.

3.6.2.1PIC Mode

PIC Mode is software compatible with the PC/AT because it actually employs the same hardware interrupt configuration. As Figure 3-2 illustrates, the hardware for PIC Mode bypasses the APIC components by using an interrupt mode configuration register (IMCR). This register controls whether the interrupt signals that reach the BSP come from the master PIC or from the local APIC. Before entering Symmetric I/O Mode, either the BIOS or the operating system must switch out of PIC Mode by changing the IMCR.

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Intel MultiProcessor manual 3.6.2.1PIC Mode, Version

Contents

Version MultiProcessor SpecificationIntel Corporation Literature Center P.O. Box Date Revision HistoryRevision Revision HistoryPage Chapter 2 System Overview Table of ContentsChapter 3 Hardware Specification Chapter 1 IntroductionChapter 5 Default Configurations Chapter 4 MP Configuration TableAppendix A System BIOS Programming Guidelines Appendix C System Compliance ChecklistAppendix E Errata Glossary Tables FiguresExamples Page 1.1 Goals 1 Introduction1.3Scope 1.2 Features of the Specification1.4 Target Audience 1.5Organization of This DocumentIS EXPECTED TO REMAIN CONSTANT 1.6 Conventions Used in This Document 1.7 For More InformationIN THE RESERVED FIELDS Version 2 System Overview2.1.1System Processors 2.1 Hardware Overview2.1.2Advanced Programmable Interrupt Controller Figure 2-2.APIC Configuration2.1.4I/O Expansion Bus 2.1.3System Memory2.3 Operating System Overview 2.2 BIOS OverviewPage 3.1 System Memory Configuration 3 Hardware SpecificationFigure 3-1.System Memory Address Map 3.2 System Memory Cacheability and ShareabilityShared by All Hardware SpecificationTable 3-1.Memory Cacheability Map Addresses3.4Locking 3.3 External Cache Subsystem3.5 Posted Memory Write 3.6 Multiprocessor Interrupt Control3.6.1APIC Architecture 3.6.2Interrupt Modes Version 3.6.2.1PIC ModeFigure 3-2.PIC Mode Figure 3-3.Virtual Wire Mode via Local APIC 3.6.2.2Virtual Wire Mode3-10 Figure 3-4.Virtual Wire Mode via I/O APICFigure 3-5.Symmetric I/O Mode 3.6.2.3Symmetric I/O Mode3.6.5APIC Memory Mapping 3.6.4Floating Point Exception Interrupt3.6.7APIC Interval Timers 3.6.8Multiple I/O APIC Configurations3.6.6APIC Identification 3.7.1System-wideRESET 3.7 RESET Support3-15 3.7.2System-wideINIT3.7.3Processor-specificINIT Version3.8 System Initial State 3.9 Support for Fault-resilientBootingFigure 4-1.MP Configuration Data Structures 4 MP Configuration TableThe following two data structures are used 4.1MP Floating Pointer Structure Figure 4-2.MP Floating Pointer StructureTable 4-1.MP Floating Pointer Structure Fields Field MultiProcessor SpecificationOffset Length4.2MP Configuration Table Header Figure 4-3.MP Configuration Table Header1CH 10H ENTRY TYPE 4.3BaseMP Configuration Table EntriesTable 4-3. BaseMP Configuration TableEntry Types 4.3.1Processor EntriesFigure 4-4.Processor Entry Table 4-4.Processor Entry Fields Model Table 4-6.Feature Flags from CPUID InstructionMP Configuration Table FamilyFigure 4-5.Bus Entry Table 4-7.Bus Entry Fields 4.3.2 Bus EntriesDescription MP Configuration TableTable 4-8.Bus Type String Values Bus Type StringTable 4-9.I/O APIC Entry Fields 4.3.3 I/O APIC Entries4.3.4 I/O Interrupt Assignment Entries I/O APIC EntryFigure 4-7.I/O Interrupt Entry Version4-13 Table 4-10.I/O Interrupt Entry Fields 4.3.5Local Interrupt Assignment Entries Table 4-11.Interrupt Type ValuesFigure 4-8.Local Interrupt Entry Length MultiProcessor SpecificationTable 4-12.Local Interrupt Entry Fields Offset in4.4Extended MP Configuration Table Entries Figure 4-9.System Address Space Entry 4.4.1System Address Space Mapping EntriesField MP Configuration TableOffset LengthSince all device settings must fall within supported System Address Space mapping for a given bus in order to be usable by the operating system, buses that do not support dynamically configurable devices i.e., ISA, EISA should support all possible addresses to that bus Figure 4-11.Bus Hierarchy Descriptor Entry 4.4.2Bus Hierarchy Descriptor EntryField Table 4-15Bus Hierarchy Descriptor Entry FieldsOffset LengthADDRESS MOD Version4-23 PREDEFINED RANGE LISTTable 4-17.Predefined Range Lists 5 Default Configurations Table 5-1.Default Configurations 5.1 Discrete APIC ConfigurationsMARK Default ConfigurationsVersion SHADED AREAS5.2 Integrated APIC Configurations MARK VersionSHADED AREAS B,C EISA BUS SPECIFIC D PCI BUS SPECIFICMultiProcessor Specification 5.3.2Level-triggeredInterrupt Support 5.3.1EISA and IRQ13The 8259A INTR output signal is connected to the LINTIN0 of all local APICs, which makes INTR dynamically routable via software. NMI is connected to the LINTIN1 of all local APICs, which makes NMI dynamically routable via software A.1 BIOS Post Initialization A System BIOS Programming GuidelinesA.2 Controlling the Application Processors A.3 Programming the APIC for Virtual Wire ModeVersion System BIOS Programming GuidelinesA.4 Constructing the MP Configuration Table Version Page B.1 Operating System Boot-up B Operating System Programming GuidelinesB.3 Interrupt Mode Initialization and Handling Example B-1.Universal Start-upAlgorithm B.4 Application Processor StartupB.4.1 USINGINIT IPI B.5 APShutdown Handling B.4.2 USINGSTARTUP IPIB.6.2 Handling TLB Invalidation B.6 Other IPI ApplicationsB.7 Spurious APIC Interrupts B.6.1 Handling Cache FlushVersion B.8 Supporting Unequal ProcessorsPage C System Compliance Checklist Any NO answer indicates non-complianceCondition Page D Multiple I/O APIC Multiple PCI Bus Systems D.1 Interrupt Routing with Multiple APICsD.1.1 Variable Interrupt Routing D.1.2 Fixed Interrupt Routing Field Multiple I/O APIC Multiple PCI Bus SystemsOffset LengthPage Version E ErrataSIGNATURE Figure 4-9.System Address Space Entry 4.4.1 System Address Space Mapping EntriesENTRY TYPE space records must also be provided 4.4.2 Bus Hierarchy Descriptor EntryTable 4-15Bus Hierarchy Descriptor Entry Fields Figure 4-11.Bus Hierarchy Descriptor EntryGlossary Glossary-2 Order Number