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Intel manual MultiProcessor Specification

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MultiProcessor Specification

should be cross-connected between the BSP and AP processors. Although the INIT pin is cross- connected between BSP and AP, a targeted INIT IPI initializes only the targeted processor, because the INIT IPI does not cause the INIT pin to change state.

The interconnection of I/O APIC interrupt lines is the same as for the 82489DX APIC configuration. However, for PCI system implementations based on the Intel PCI chipset, the PCI PIRQx lines are mapped to the ISA IRQx via a mapping register. This type of implementation makes PCI interrupt lines appear as ISA interrupt lines, which are transparent to the operating system. All PCI systems defined in the default configurations are of this type. No I/O interrupt assignment entries are declared for PCI interrupts, as described in Section 4.3.4.

5.3 Assignment of I/O Interrupts to the APIC I/O Unit

The typical APIC I/O unit has 16 general-purpose interrupt inputs. Table 5-2 shows how the interrupt request line (IRQ) assignments are connected to the I/O APIC in each of the default configurations.

Table 5-2. Default Configuration Interrupt Assignments

First I/O
APIC	Config	Config	Config	Config	Config	Config	Config
INTINx	1	2	3	4	5	6	7	Comments

INTIN0	8259A	8259A	8259A	8259A	8259A	8259A	N/C	INTR output from
	INTR	INTR	INTR	INTR	INTR	INTR		master 8259A or
								equivalent

INTIN1	IRQ1	IRQ1	IRQ1	IRQ1	IRQ1	IRQ1	IRQ1	Keyboard controller
								buffer full

INTIN2	IRQ0	N/C	IRQ0	IRQ0	IRQ0	IRQ0	IRQ0	8254 Timer

INTIN3	IRQ3	IRQ3	IRQ3	IRQ3	IRQ3	IRQ3	IRQ3

INTIN4	IRQ4	IRQ4	IRQ4	IRQ4	IRQ4	IRQ4	IRQ4

INTIN5	IRQ5	IRQ5	IRQ5	IRQ5	IRQ5	IRQ5	IRQ5

INTIN6	IRQ6	IRQ6	IRQ6	IRQ6	IRQ6	IRQ6	IRQ6

INTIN7	IRQ7	IRQ7	IRQ7	IRQ7	IRQ7	IRQ7	IRQ7

INTIN8	IRQ8	IRQ8	IRQ8	IRQ8	IRQ8	IRQ8	IRQ8	Real time clock

INTIN9	IRQ9	IRQ9	IRQ9	IRQ9	IRQ9	IRQ9	IRQ9

INTIN10	IRQ10	IRQ10	IRQ10	IRQ10	IRQ10	IRQ10	IRQ10

INTIN11	IRQ11	IRQ11	IRQ11	IRQ11	IRQ11	IRQ11	IRQ11

INTIN12	IRQ12	IRQ12	IRQ12	IRQ12	IRQ12	IRQ12	IRQ12

INTIN13	IRQ13	N/C	IRQ13	IRQ13	IRQ13	IRQ13	IRQ13	Floating point
								exception and
								DMA chaining

INTIN14	IRQ14	IRQ14	IRQ14	IRQ14	IRQ14	IRQ14	IRQ14

INTIN15	IRQ15	IRQ15	IRQ15	IRQ15	IRQ15	IRQ15	IRQ15

NOTE:

N/C designates not connected.

5-6	Version 1.4

Image 66

Intel manual MultiProcessor Specification

Contents

MultiProcessor Specification VersionIntel Corporation Literature Center P.O. Box Revision History Revision HistoryRevision DatePage Chapter 1 Introduction Table of ContentsChapter 3 Hardware Specification Chapter 2 System OverviewChapter 4 MP Configuration Table Chapter 5 Default ConfigurationsAppendix A System BIOS Programming Guidelines Appendix C System Compliance ChecklistAppendix E Errata Glossary Figures TablesExamples Page 1 Introduction 1.1 Goals1.2 Features of the Specification 1.3Scope1.4 Target Audience 1.5Organization of This DocumentIS EXPECTED TO REMAIN CONSTANT 1.6 Conventions Used in This Document 1.7 For More InformationIN THE RESERVED FIELDS 2 System Overview Version2.1 Hardware Overview 2.1.1System ProcessorsFigure 2-2.APIC Configuration 2.1.2Advanced Programmable Interrupt Controller2.1.3System Memory 2.1.4I/O Expansion Bus2.2 BIOS Overview 2.3 Operating System OverviewPage 3 Hardware Specification 3.1 System Memory Configuration3.2 System Memory Cacheability and Shareability Figure 3-1.System Memory Address MapAddresses Hardware SpecificationTable 3-1.Memory Cacheability Map Shared by All3.3 External Cache Subsystem 3.4Locking3.5 Posted Memory Write 3.6 Multiprocessor Interrupt Control3.6.1APIC Architecture 3.6.2Interrupt Modes 3.6.2.1PIC Mode VersionFigure 3-2.PIC Mode 3.6.2.2Virtual Wire Mode Figure 3-3.Virtual Wire Mode via Local APICFigure 3-4.Virtual Wire Mode via I/O APIC 3-103.6.2.3Symmetric I/O Mode Figure 3-5.Symmetric I/O Mode3.6.4Floating Point Exception Interrupt 3.6.5APIC Memory Mapping3.6.7APIC Interval Timers 3.6.8Multiple I/O APIC Configurations3.6.6APIC Identification 3.7 RESET Support 3.7.1System-wideRESETVersion 3.7.2System-wideINIT3.7.3Processor-specificINIT 3-153.9 Support for Fault-resilientBooting 3.8 System Initial State4 MP Configuration Table Figure 4-1.MP Configuration Data StructuresThe following two data structures are used 4.1MP Floating Pointer Structure Figure 4-2.MP Floating Pointer StructureTable 4-1.MP Floating Pointer Structure Fields Length MultiProcessor SpecificationOffset Field4.2MP Configuration Table Header Figure 4-3.MP Configuration Table Header1CH 10H 4.3BaseMP Configuration Table Entries ENTRY TYPETable 4-3. BaseMP Configuration TableEntry Types 4.3.1Processor EntriesFigure 4-4.Processor Entry Table 4-4.Processor Entry Fields Family Table 4-6.Feature Flags from CPUID InstructionMP Configuration Table Model4.3.2 Bus Entries Figure 4-5.Bus Entry Table 4-7.Bus Entry FieldsBus Type String MP Configuration TableTable 4-8.Bus Type String Values DescriptionI/O APIC Entry 4.3.3 I/O APIC Entries4.3.4 I/O Interrupt Assignment Entries Table 4-9.I/O APIC Entry FieldsFigure 4-7.I/O Interrupt Entry Version4-13 Table 4-10.I/O Interrupt Entry Fields 4.3.5Local Interrupt Assignment Entries Table 4-11.Interrupt Type ValuesFigure 4-8.Local Interrupt Entry Offset in MultiProcessor SpecificationTable 4-12.Local Interrupt Entry Fields Length4.4Extended MP Configuration Table Entries 4.4.1System Address Space Mapping Entries Figure 4-9.System Address Space EntryLength MP Configuration TableOffset FieldSince all device settings must fall within supported System Address Space mapping for a given bus in order to be usable by the operating system, buses that do not support dynamically configurable devices i.e., ISA, EISA should support all possible addresses to that bus 4.4.2Bus Hierarchy Descriptor Entry Figure 4-11.Bus Hierarchy Descriptor EntryLength Table 4-15Bus Hierarchy Descriptor Entry FieldsOffset FieldPREDEFINED RANGE LIST Version4-23 ADDRESS MODTable 4-17.Predefined Range Lists 5 Default Configurations 5.1 Discrete APIC Configurations Table 5-1.Default ConfigurationsSHADED AREAS Default ConfigurationsVersion MARK5.2 Integrated APIC Configurations B,C EISA BUS SPECIFIC D PCI BUS SPECIFIC VersionSHADED AREAS MARKMultiProcessor Specification 5.3.1EISA and IRQ13 5.3.2Level-triggeredInterrupt SupportThe 8259A INTR output signal is connected to the LINTIN0 of all local APICs, which makes INTR dynamically routable via software. NMI is connected to the LINTIN1 of all local APICs, which makes NMI dynamically routable via software A System BIOS Programming Guidelines A.1 BIOS Post InitializationA.3 Programming the APIC for Virtual Wire Mode A.2 Controlling the Application ProcessorsSystem BIOS Programming Guidelines VersionA.4 Constructing the MP Configuration Table Version Page B Operating System Programming Guidelines B.1 Operating System Boot-upB.3 Interrupt Mode Initialization and Handling B.4 Application Processor Startup Example B-1.Universal Start-upAlgorithmB.4.1 USINGINIT IPI B.4.2 USINGSTARTUP IPI B.5 APShutdown HandlingB.6.1 Handling Cache Flush B.6 Other IPI ApplicationsB.7 Spurious APIC Interrupts B.6.2 Handling TLB InvalidationB.8 Supporting Unequal Processors VersionPage C System Compliance Checklist Any NO answer indicates non-complianceCondition Page D Multiple I/O APIC Multiple PCI Bus Systems D.1 Interrupt Routing with Multiple APICsD.1.1 Variable Interrupt Routing D.1.2 Fixed Interrupt Routing Length Multiple I/O APIC Multiple PCI Bus SystemsOffset FieldPage E Errata VersionSIGNATURE 4.4.1 System Address Space Mapping Entries Figure 4-9.System Address Space EntryENTRY TYPE 4.4.2 Bus Hierarchy Descriptor Entry space records must also be providedFigure 4-11.Bus Hierarchy Descriptor Entry Table 4-15Bus Hierarchy Descriptor Entry FieldsGlossary Glossary-2 Order Number