Virtual Wire Mode via I/O Apic | Intel MultiProcessor manual

MultiProcessor Specification

Figure 3-3 shows how Virtual Wire Mode can be implemented through the BSP’s local APIC. It is also permissible to program the I/O APIC for Virtual Wire Mode, as shown in Figure 3-4. In this case the interrupt signal passes through both the I/O APIC and the BSP’s local APIC.

BSP		AP1		AP2
CPU 1		CPU 2		CPU 3

	NMI	INTR		NMI INTR			NMI	INTR
		LOCAL		LOCAL				LOCAL
REG.		APIC		APIC				APIC
REG.		1		2					3
MARK	LINTIN0		LINTIN1	LINTIN0	LINTIN1		LINTIN0		LINTIN1
	LINTIN0		LINTIN1	LINTIN0	LINTIN1		LINTIN0		LINTIN1
LINTIN1
LINTIN0
RESET
ICC BUS
NMI
				8259A-
				EQUIVALENT		INTR
				PICS
INTERRUPT INPUTS									I/O
INTERRUPT INPUTS									APIC
									APIC

SHADED AREAS INDICATE UNUSED CIRCUITS. DOTTED LINE SHOWS INTERRUPT PATH.

Figure 3-4. Virtual Wire Mode via I/O APIC

3-10	Version 1.4

Image 30

Intel MultiProcessor manual Virtual Wire Mode via I/O Apic

Contents

MultiProcessor Specification Copyright 1993-1997. Intel Corporation, All Rights Reserved Revision History Revision Revision History DatePage Table of Contents MP Configuration Table Default ConfigurationsContents Appendix a System Bios Programming Guidelines Appendix B Operating System Programming GuidelinesAppendix E Errata Glossary Figures Tables Examples Page Goals Conceptual Overview Features of the Specification MultiProcessor SpecificationScope Document Organization Target AudienceOrganization of This Document Introduction Conventions Used in This Document For More Information System Overview Hardware Overview System Processors Advanced Programmable Interrupt Controller System Overview System Memory 4 I/O Expansion Bus Bios Overview Operating System OverviewPage Hardware Specification System Memory Configuration System Memory Cacheability and Shareability System Memory Address Map Hardware Specification Memory Cacheability Map External Cache Subsystem Locking Posted Memory Write Multiprocessor Interrupt ControlApic Architecture Interrupt Modes Apic Versions PIC Mode PIC Mode Virtual Wire Mode Virtual Wire Mode via Local Apic Virtual Wire Mode via I/O Apic Symmetric I/O Mode Symmetric I/O Mode Assignment of System Interrupts to the Apic Local Unit Floating Point Exception InterruptApic Memory Mapping Apic Interval Timers Apic Identification Reset Support System-wide Reset System-wide Init Processor-specific Init Support for Fault-resilient Booting System Initial State MP Configuration Table MultiProcessor Specification MP Configuration Table MP Floating Pointer StructureOffset Length Field Bytesbits in bits Description Information Byte MP FeatureOffset Length Field Bytesbits Bits Description Information Bytes MP Configuration Table Header MP Configuration Table Header Base MP Configuration Table Entries MP Configuration Table Header FieldsOffset Length Field Bytes Bits Description Length Entry Description Entry Type Code Bytes Comments Base MP Configuration Table Entry TypesProcessor Entries Apic Processor Entry Fields Family Model Stepping a Description Feature Flags from Cpuid InstructionIntel486 and Pentium Processor Signatures Bit Name Description Comments BUS Type Bus EntriesBUS ID String Bus Type String Values Bus Type String Description Apic Entry 3 I/O Apic Entries4 I/O Interrupt Assignment Entries I/O Apic Entry Fields I/O Interrupt Entry 10. I/O Interrupt Entry Fields Local Interrupt Assignment Entries 11. Interrupt Type ValuesInterrupt Type Description Comments Destination Local Apic 12. Local Interrupt Entry FieldsDestination Local Apic ID LINTIN# Extended MP Configuration Table Entries System Address Space Mapping Entries 14. System Address Space Mapping Entry Fields 10. Example System with Multiple Bus Types and Bridge Types Bus Hierarchy Descriptor Entry Compatibility Bus Address Space Modifier Entry 12. Compatibility Bus Address Space Modifier Entry 16. Compatibility Bus Address Space Modifier Entry Fields Default Configurations Default Number Bus Discrete Apic ConfigurationsDefault Configurations Config Code CPUs Type Variant Schematic Default Configuration for Discrete Apic Default Configurations Integrated Apic Configurations Default Configuration for Integrated Apic Assignment of I/O Interrupts to the Apic I/O Unit Default Configuration Interrupt AssignmentsConfig INTINx Comments First I/O Eisa and IRQ13 All Local APICs Config LINTINx CommentsAssignment of System Interrupts to the Apic Local Unit Level-triggered Interrupt Support MultiProcessor Specification System Bios Programming Guidelines Bios Post Initialization Programming the Apic for Virtual Wire Mode Controlling the Application Processors Example A-1. Programming Local Apic for Virtual Wire Mode System Bios Programming Guidelines Constructing the MP Configuration Table NMI System Bios Programming Guidelines Page Operating System Boot-up Operating System Programming Guidelines Operating System Booting and Self-configuration Interrupt Mode Initialization and Handling Application Processor Startup Operating System Programming Guidelines Using Init IPI Using Startup IPI AP Shutdown Handling Handling Cache Flush Other IPI ApplicationsSpurious Apic Interrupts Handling TLB Invalidation Supporting Unequal Processors Page System Compliance Checklist Page Interrupt Routing with Multiple APICs Variable Interrupt Routing Fixed Interrupt Routing Multiple I/O Apic Multiple PCI Bus Systems Bus Entries in Systems with More Than One PCI BusI/O Interrupt Assignment Entries for PCI Devices INTD#Page Errata 126 System Address Space Mapping Entries System Address Space Entry Address Type 14. System Address Space Mapping Entry FieldsEntry Length Address Base Bus Hierarchy Descriptor Entry Space records must also be provided BUS Informationsd Parent BUS Glossary Glossary-2 Order Number