Manuals
/
Intel
/
Computer Equipment
/
Computer Hardware
Intel
MultiProcessor manual Order Number
Models:
MultiProcessor
1
97
97
Download
97 pages
61.7 Kb
90
91
92
93
94
95
96
97
<
>
Specs
MP Configuration Table
3.6.2.2Virtual Wire Mode
RESET Support
Support for Fault-resilientBooting
3.6.7APIC Interval Timers
The 8259A INTR output signal is connected to the LINTIN0 of all local APICs, which makes INTR dynamically routable via software. NMI is connected to the LINTIN1 of all local APICs, which makes NMI dynamically routable via software
Checklist
BIOS Overview
6.Feature Flags from CPUID Instruction
Page 97
Image 97
Order Number:
242016-00
6
Printed in U.S.A.
Page 96
Page 97
Image 97
Page 96
Contents
Version
MultiProcessor Specification
Intel Corporation Literature Center P.O. Box
Revision
Revision History
Revision History
Date
Page
Chapter 3 Hardware Specification
Table of Contents
Chapter 1 Introduction
Chapter 2 System Overview
Chapter 5 Default Configurations
Chapter 4 MP Configuration Table
Appendix C System Compliance Checklist
Appendix A System BIOS Programming Guidelines
Appendix E Errata Glossary
Tables
Figures
Examples
Page
1.1 Goals
1 Introduction
1.3Scope
1.2 Features of the Specification
1.5Organization of This Document
1.4 Target Audience
IS EXPECTED TO REMAIN CONSTANT
1.7 For More Information
1.6 Conventions Used in This Document
IN THE RESERVED FIELDS
Version
2 System Overview
2.1.1System Processors
2.1 Hardware Overview
2.1.2Advanced Programmable Interrupt Controller
Figure 2-2.APIC Configuration
2.1.4I/O Expansion Bus
2.1.3System Memory
2.3 Operating System Overview
2.2 BIOS Overview
Page
3.1 System Memory Configuration
3 Hardware Specification
Figure 3-1.System Memory Address Map
3.2 System Memory Cacheability and Shareability
Table 3-1.Memory Cacheability Map
Hardware Specification
Addresses
Shared by All
3.4Locking
3.3 External Cache Subsystem
3.6 Multiprocessor Interrupt Control
3.5 Posted Memory Write
3.6.1APIC Architecture
3.6.2Interrupt Modes
Version
3.6.2.1PIC Mode
Figure 3-2.PIC Mode
Figure 3-3.Virtual Wire Mode via Local APIC
3.6.2.2Virtual Wire Mode
3-10
Figure 3-4.Virtual Wire Mode via I/O APIC
Figure 3-5.Symmetric I/O Mode
3.6.2.3Symmetric I/O Mode
3.6.5APIC Memory Mapping
3.6.4Floating Point Exception Interrupt
3.6.8Multiple I/O APIC Configurations
3.6.7APIC Interval Timers
3.6.6APIC Identification
3.7.1System-wideRESET
3.7 RESET Support
3.7.3Processor-specificINIT
3.7.2System-wideINIT
Version
3-15
3.8 System Initial State
3.9 Support for Fault-resilientBooting
Figure 4-1.MP Configuration Data Structures
4 MP Configuration Table
The following two data structures are used
Figure 4-2.MP Floating Pointer Structure
4.1MP Floating Pointer Structure
Table 4-1.MP Floating Pointer Structure Fields
Offset
MultiProcessor Specification
Length
Field
Figure 4-3.MP Configuration Table Header
4.2MP Configuration Table Header
1CH 10H
ENTRY TYPE
4.3BaseMP Configuration Table Entries
4.3.1Processor Entries
Table 4-3. BaseMP Configuration TableEntry Types
Figure 4-4.Processor Entry
Table 4-4.Processor Entry Fields
MP Configuration Table
Table 4-6.Feature Flags from CPUID Instruction
Family
Model
Figure 4-5.Bus Entry Table 4-7.Bus Entry Fields
4.3.2 Bus Entries
Table 4-8.Bus Type String Values
MP Configuration Table
Bus Type String
Description
4.3.4 I/O Interrupt Assignment Entries
4.3.3 I/O APIC Entries
I/O APIC Entry
Table 4-9.I/O APIC Entry Fields
Version
Figure 4-7.I/O Interrupt Entry
4-13
Table 4-10.I/O Interrupt Entry Fields
Table 4-11.Interrupt Type Values
4.3.5Local Interrupt Assignment Entries
Figure 4-8.Local Interrupt Entry
Table 4-12.Local Interrupt Entry Fields
MultiProcessor Specification
Offset in
Length
4.4Extended MP Configuration Table Entries
Figure 4-9.System Address Space Entry
4.4.1System Address Space Mapping Entries
Offset
MP Configuration Table
Length
Field
Since all device settings must fall within supported System Address Space mapping for a given bus in order to be usable by the operating system, buses that do not support dynamically configurable devices i.e., ISA, EISA should support all possible addresses to that bus
Figure 4-11.Bus Hierarchy Descriptor Entry
4.4.2Bus Hierarchy Descriptor Entry
Offset
Table 4-15Bus Hierarchy Descriptor Entry Fields
Length
Field
4-23
Version
PREDEFINED RANGE LIST
ADDRESS MOD
Table 4-17.Predefined Range Lists
5 Default Configurations
Table 5-1.Default Configurations
5.1 Discrete APIC Configurations
Version
Default Configurations
SHADED AREAS
MARK
5.2 Integrated APIC Configurations
SHADED AREAS
Version
B,C EISA BUS SPECIFIC D PCI BUS SPECIFIC
MARK
MultiProcessor Specification
5.3.2Level-triggeredInterrupt Support
5.3.1EISA and IRQ13
The 8259A INTR output signal is connected to the LINTIN0 of all local APICs, which makes INTR dynamically routable via software. NMI is connected to the LINTIN1 of all local APICs, which makes NMI dynamically routable via software
A.1 BIOS Post Initialization
A System BIOS Programming Guidelines
A.2 Controlling the Application Processors
A.3 Programming the APIC for Virtual Wire Mode
Version
System BIOS Programming Guidelines
A.4 Constructing the MP Configuration Table
Version
Page
B.1 Operating System Boot-up
B Operating System Programming Guidelines
B.3 Interrupt Mode Initialization and Handling
Example B-1.Universal Start-upAlgorithm
B.4 Application Processor Startup
B.4.1 USINGINIT IPI
B.5 APShutdown Handling
B.4.2 USINGSTARTUP IPI
B.7 Spurious APIC Interrupts
B.6 Other IPI Applications
B.6.1 Handling Cache Flush
B.6.2 Handling TLB Invalidation
Version
B.8 Supporting Unequal Processors
Page
Any NO answer indicates non-compliance
C System Compliance Checklist
Condition
Page
D.1 Interrupt Routing with Multiple APICs
D Multiple I/O APIC Multiple PCI Bus Systems
D.1.1 Variable Interrupt Routing
D.1.2 Fixed Interrupt Routing
Offset
Multiple I/O APIC Multiple PCI Bus Systems
Length
Field
Page
Version
E Errata
SIGNATURE
Figure 4-9.System Address Space Entry
4.4.1 System Address Space Mapping Entries
ENTRY TYPE
space records must also be provided
4.4.2 Bus Hierarchy Descriptor Entry
Table 4-15Bus Hierarchy Descriptor Entry Fields
Figure 4-11.Bus Hierarchy Descriptor Entry
Glossary
Glossary-2
Order Number
