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| Processor | 0 | 20 | One entry per processor. | |
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| Bus | 1 | 8 | One entry per bus. | |
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| I/O APIC | 2 | 8 | One entry per I/O APIC. | |
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| I/O Interrupt Assignment | 3 | 8 | One entry per bus interrupt source. | |
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| Local Interrupt Assignment | 4 | 8 | One entry per system interrupt | |
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*All other type codes are reserved.
4.3.1Processor Entries
Figure 4-4 shows the format of each processor entry, and Table 4-4 defines the fields.
31 | 28 27 | 24 23 | 20 19 | 16 15 | 12 11 | 8 | 7 | 4 | 3 | 0 |
RESERVED
RESERVED
FEATURE FLAGS
CPU SIGNATURE
| CPU FLAGS |
| LOCAL APIC |
| LOCAL APIC ID |
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RESERVED | P | N |
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31 | 28 27 | 24 23 | 20 19 | 16 15 | 12 11 | 8 | 7 | 4 | 3 | 0 | |||
10H
0CH
08H
04H
00H
Figure 4-4. Processor Entry
In systems that use the MP configuration table, the only restriction placed on the assignment of APIC IDs is that they be unique. They do not need to be consecutive. For example, it is possible for only APIC IDs 0, 2, and 4 to be present.
Version 1.4 |
