Intel manual 12.Local Interrupt Entry Fields, MultiProcessor Specification, Offset in, Length

MultiProcessor Specification

Table 4-12. Local Interrupt Entry Fields

	Offset (in	Length
Field	bytes:bits)	(in bits)	Description
ENTRY TYPE	0	8	Entry type 4 identifies a local interrupt
			entry.
INTERRUPT TYPE	1	8	See Table 4-11 for values
PO	2:0	2	Polarity of APIC local input signals:
			00 =	Conforms to
				specifications of bus
				(for example, EISA is
				active-low for level
				triggered interrupts)
			01 =	Active high
			10 =	Reserved
			11 =	Active low
			Must be 00 if the 82489DX is used.
EL	2:2	2	Trigger mode of APIC local input signals:
			00 =	Conforms to
				specifications of bus
				(for example, ISA is
				edge triggered)
			01 =	Edge-triggered
			10 =	Reserved
			11 =	Level-triggered
SOURCE BUS ID	4	8	Identifies the bus from which the interrupt
			signal came.
SOURCE BUS IRQ	5	8	Identifies the interrupt signal from the
			source bus. Values are mapped onto
			source bus signals, starting from zero. A
			value of 0, for example, would indicate
			IRQ0 of an ISA bus. See Section D.3 for
			PCI bus semantics.
DESTINATION LOCAL APIC ID	6	8	Identifies the local APIC to which the
			signal is connected. If the ID is 0FFh, the
			signal is connected to all local APICs.
DESTINATION LOCAL APIC	7	8	Identifies the LINTINn pin to which the
LINTIN#			signal is connected, where n = 0 or 1.

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