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Intel MultiProcessor 1.Memory Cacheability Map, Hardware Specification, Addresses, Shared by All

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Hardware Specification

								Hardware Specification
		Table 3-1. Memory Cacheability Map						Hardware Specification
		Table 3-1. Memory Cacheability Map

		Addresses				Shared by All
		(in hex)		Size	Description	Processors?	Cacheable?	Comment

		0000_0000h –		640KB	Main memory	Yes	Yes
		0009_FFFFh

		000A_0000h –		128KB	Display buffer for	Yes	No
		000B_FFFFh			video adapters

		000C_0000h –		128KB ROM BIOS for add-on		Yes	Yes
		000D_FFFFh			cards

		000E_0000h –		128KB	System ROM BIOS	Yes	Yes
		000F_FFFFh

		0010_0000h –			Main memory	Yes	Yes	Maximum address
		0FEBF_FFFFh						depends on total memory
								installed in the system.

		Not specified.			Memory-mapped I/O	Yes2	Not	Top unused memory
					devices		specified

		0FEC0_0000h –			APIC I/O unit	Yes	No	Refer to the register
		0FECF_FFFFh1						description in the APIC
								data book.

		0FED0_0000h –			Reserved for	Yes2	Not
		0FEDF_FFFFh			memory-mapped I/O		specified
					devices

		0FEE0_0000h-			APIC Local Unit	No	No	Refer to the register
		0FEEF_FFFFh1						description in the APIC
								data book.

		0FEF0_0000h –			Reserved for	Yes2	Not
		0FFFD_FFFFh			memory-mapped I/O		specified
					devices

		0FFFE_0000h –		128KB	Initialization ROM	Yes	Not
		0FFFF_FFFFh					specified

NOTES:

1.These addresses are part of this specification. The other address regions in this table are shown for reference only, and should not be construed as the sole definition of a PC/AT-compatible address space format or cache.

2.Any memory-mapped device should be shareable unless the nature of the device is that there is one device per processor.

Version 1.4

3-3

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Intel MultiProcessor 1.Memory Cacheability Map, Hardware Specification, Addresses, Shared by All, in hex, Size, Cacheable?

Contents

Version MultiProcessor SpecificationIntel Corporation Literature Center P.O. Box Date Revision HistoryRevision Revision HistoryPage Chapter 2 System Overview Table of ContentsChapter 3 Hardware Specification Chapter 1 IntroductionChapter 5 Default Configurations Chapter 4 MP Configuration TableAppendix E Errata Glossary Appendix A System BIOS Programming GuidelinesAppendix C System Compliance Checklist Tables FiguresExamples Page 1.1 Goals 1 Introduction1.3Scope 1.2 Features of the SpecificationIS EXPECTED TO REMAIN CONSTANT 1.4 Target Audience1.5Organization of This Document IN THE RESERVED FIELDS 1.6 Conventions Used in This Document1.7 For More Information Version 2 System Overview2.1.1System Processors 2.1 Hardware Overview2.1.2Advanced Programmable Interrupt Controller Figure 2-2.APIC Configuration2.1.4I/O Expansion Bus 2.1.3System Memory2.3 Operating System Overview 2.2 BIOS OverviewPage 3.1 System Memory Configuration 3 Hardware SpecificationFigure 3-1.System Memory Address Map 3.2 System Memory Cacheability and ShareabilityShared by All Hardware SpecificationTable 3-1.Memory Cacheability Map Addresses3.4Locking 3.3 External Cache Subsystem3.6.1APIC Architecture 3.5 Posted Memory Write3.6 Multiprocessor Interrupt Control 3.6.2Interrupt Modes Version 3.6.2.1PIC ModeFigure 3-2.PIC Mode Figure 3-3.Virtual Wire Mode via Local APIC 3.6.2.2Virtual Wire Mode3-10 Figure 3-4.Virtual Wire Mode via I/O APICFigure 3-5.Symmetric I/O Mode 3.6.2.3Symmetric I/O Mode3.6.5APIC Memory Mapping 3.6.4Floating Point Exception Interrupt3.6.6APIC Identification 3.6.7APIC Interval Timers3.6.8Multiple I/O APIC Configurations 3.7.1System-wideRESET 3.7 RESET Support3-15 3.7.2System-wideINIT3.7.3Processor-specificINIT Version3.8 System Initial State 3.9 Support for Fault-resilientBootingFigure 4-1.MP Configuration Data Structures 4 MP Configuration TableThe following two data structures are used Table 4-1.MP Floating Pointer Structure Fields 4.1MP Floating Pointer StructureFigure 4-2.MP Floating Pointer Structure Field MultiProcessor SpecificationOffset Length1CH 10H 4.2MP Configuration Table HeaderFigure 4-3.MP Configuration Table Header ENTRY TYPE 4.3BaseMP Configuration Table EntriesFigure 4-4.Processor Entry Table 4-3. BaseMP Configuration TableEntry Types4.3.1Processor Entries Table 4-4.Processor Entry Fields Model Table 4-6.Feature Flags from CPUID InstructionMP Configuration Table FamilyFigure 4-5.Bus Entry Table 4-7.Bus Entry Fields 4.3.2 Bus EntriesDescription MP Configuration TableTable 4-8.Bus Type String Values Bus Type StringTable 4-9.I/O APIC Entry Fields 4.3.3 I/O APIC Entries4.3.4 I/O Interrupt Assignment Entries I/O APIC Entry4-13 Figure 4-7.I/O Interrupt EntryVersion Table 4-10.I/O Interrupt Entry Fields Figure 4-8.Local Interrupt Entry 4.3.5Local Interrupt Assignment EntriesTable 4-11.Interrupt Type Values Length MultiProcessor SpecificationTable 4-12.Local Interrupt Entry Fields Offset in4.4Extended MP Configuration Table Entries Figure 4-9.System Address Space Entry 4.4.1System Address Space Mapping EntriesField MP Configuration TableOffset LengthSince all device settings must fall within supported System Address Space mapping for a given bus in order to be usable by the operating system, buses that do not support dynamically configurable devices i.e., ISA, EISA should support all possible addresses to that bus Figure 4-11.Bus Hierarchy Descriptor Entry 4.4.2Bus Hierarchy Descriptor EntryField Table 4-15Bus Hierarchy Descriptor Entry FieldsOffset LengthADDRESS MOD Version4-23 PREDEFINED RANGE LISTTable 4-17.Predefined Range Lists 5 Default Configurations Table 5-1.Default Configurations 5.1 Discrete APIC ConfigurationsMARK Default ConfigurationsVersion SHADED AREAS5.2 Integrated APIC Configurations MARK VersionSHADED AREAS B,C EISA BUS SPECIFIC D PCI BUS SPECIFICMultiProcessor Specification 5.3.2Level-triggeredInterrupt Support 5.3.1EISA and IRQ13The 8259A INTR output signal is connected to the LINTIN0 of all local APICs, which makes INTR dynamically routable via software. NMI is connected to the LINTIN1 of all local APICs, which makes NMI dynamically routable via software A.1 BIOS Post Initialization A System BIOS Programming GuidelinesA.2 Controlling the Application Processors A.3 Programming the APIC for Virtual Wire ModeVersion System BIOS Programming GuidelinesA.4 Constructing the MP Configuration Table Version Page B.1 Operating System Boot-up B Operating System Programming GuidelinesB.3 Interrupt Mode Initialization and Handling Example B-1.Universal Start-upAlgorithm B.4 Application Processor StartupB.4.1 USINGINIT IPI B.5 APShutdown Handling B.4.2 USINGSTARTUP IPIB.6.2 Handling TLB Invalidation B.6 Other IPI ApplicationsB.7 Spurious APIC Interrupts B.6.1 Handling Cache FlushVersion B.8 Supporting Unequal ProcessorsPage Condition C System Compliance ChecklistAny NO answer indicates non-compliance Page D.1.1 Variable Interrupt Routing D Multiple I/O APIC Multiple PCI Bus SystemsD.1 Interrupt Routing with Multiple APICs D.1.2 Fixed Interrupt Routing Field Multiple I/O APIC Multiple PCI Bus SystemsOffset LengthPage Version E ErrataSIGNATURE Figure 4-9.System Address Space Entry 4.4.1 System Address Space Mapping EntriesENTRY TYPE space records must also be provided 4.4.2 Bus Hierarchy Descriptor EntryTable 4-15Bus Hierarchy Descriptor Entry Fields Figure 4-11.Bus Hierarchy Descriptor EntryGlossary Glossary-2 Order Number