Memory Cacheability Map | Intel MultiProcessor specs

								Hardware Specification
		Table 3-1. Memory Cacheability Map						Hardware Specification
		Table 3-1. Memory Cacheability Map

		Addresses				Shared by All
		(in hex)		Size	Description	Processors?	Cacheable?	Comment

		0000_0000h –		640KB	Main memory	Yes	Yes
		0009_FFFFh

		000A_0000h –		128KB	Display buffer for	Yes	No
		000B_FFFFh			video adapters

		000C_0000h –		128KB ROM BIOS for add-on		Yes	Yes
		000D_FFFFh			cards

		000E_0000h –		128KB	System ROM BIOS	Yes	Yes
		000F_FFFFh

		0010_0000h –			Main memory	Yes	Yes	Maximum address
		0FEBF_FFFFh						depends on total memory
								installed in the system.

		Not specified.			Memory-mapped I/O	Yes2	Not	Top unused memory
					devices		specified

		0FEC0_0000h –			APIC I/O unit	Yes	No	Refer to the register
		0FECF_FFFFh1						description in the APIC
								data book.

		0FED0_0000h –			Reserved for	Yes2	Not
		0FEDF_FFFFh			memory-mapped I/O		specified
					devices

		0FEE0_0000h-			APIC Local Unit	No	No	Refer to the register
		0FEEF_FFFFh1						description in the APIC
								data book.

		0FEF0_0000h –			Reserved for	Yes2	Not
		0FFFD_FFFFh			memory-mapped I/O		specified
					devices

		0FFFE_0000h –		128KB	Initialization ROM	Yes	Not
		0FFFF_FFFFh					specified

NOTES:

1.These addresses are part of this specification. The other address regions in this table are shown for reference only, and should not be construed as the sole definition of a PC/AT-compatible address space format or cache.

2.Any memory-mapped device should be shareable unless the nature of the device is that there is one device per processor.

Version 1.4

3-3

Image 23

Intel MultiProcessor manual Memory Cacheability Map, Hardware Specification

Contents

MultiProcessor Specification Copyright 1993-1997. Intel Corporation, All Rights Reserved Revision Revision History Date Revision HistoryPage Table of Contents Contents MP Configuration TableDefault Configurations Appendix E Errata Glossary Appendix a System Bios Programming GuidelinesAppendix B Operating System Programming Guidelines Tables Figures Examples Page Conceptual Overview Goals Scope Features of the SpecificationMultiProcessor Specification Introduction Target AudienceOrganization of This Document Document Organization For More Information Conventions Used in This Document System Overview System Processors Hardware Overview System Overview Advanced Programmable Interrupt Controller 4 I/O Expansion Bus System Memory Operating System Overview Bios OverviewPage System Memory Configuration Hardware Specification System Memory Address Map System Memory Cacheability and Shareability Memory Cacheability Map Hardware Specification Locking External Cache Subsystem Apic Architecture Posted Memory WriteMultiprocessor Interrupt Control Apic Versions Interrupt Modes PIC Mode PIC Mode Virtual Wire Mode via Local Apic Virtual Wire Mode Virtual Wire Mode via I/O Apic Symmetric I/O Mode Symmetric I/O Mode Apic Memory Mapping Assignment of System Interrupts to the Apic Local UnitFloating Point Exception Interrupt Apic Identification Apic Interval Timers System-wide Reset Reset Support Processor-specific Init System-wide Init System Initial State Support for Fault-resilient Booting MP Configuration Table MultiProcessor Specification Offset Length Field Bytesbits in bits Description MP Configuration TableMP Floating Pointer Structure Information Bytes MP FeatureOffset Length Field Bytesbits Bits Description Information Byte MP Configuration Table Header MP Configuration Table Header Offset Length Field Bytes Bits Description Base MP Configuration Table EntriesMP Configuration Table Header Fields Apic Base MP Configuration Table Entry TypesProcessor Entries Length Entry Description Entry Type Code Bytes Comments Processor Entry Fields Bit Name Description Comments Feature Flags from Cpuid InstructionIntel486 and Pentium Processor Signatures Family Model Stepping a Description String Bus EntriesBUS ID BUS Type Bus Type String Description Bus Type String Values I/O Apic Entry Fields 3 I/O Apic Entries4 I/O Interrupt Assignment Entries Apic Entry I/O Interrupt Entry 10. I/O Interrupt Entry Fields Interrupt Type Description Comments Local Interrupt Assignment Entries11. Interrupt Type Values LINTIN# 12. Local Interrupt Entry FieldsDestination Local Apic ID Destination Local Apic Extended MP Configuration Table Entries System Address Space Mapping Entries 14. System Address Space Mapping Entry Fields 10. Example System with Multiple Bus Types and Bridge Types Bus Hierarchy Descriptor Entry Compatibility Bus Address Space Modifier Entry 12. Compatibility Bus Address Space Modifier Entry 16. Compatibility Bus Address Space Modifier Entry Fields Default Configurations Config Code CPUs Type Variant Schematic Discrete Apic ConfigurationsDefault Configurations Default Number Bus Default Configurations Default Configuration for Discrete Apic Integrated Apic Configurations Default Configuration for Integrated Apic First I/O Default Configuration Interrupt AssignmentsConfig INTINx Comments Assignment of I/O Interrupts to the Apic I/O Unit Level-triggered Interrupt Support All Local APICs Config LINTINx CommentsAssignment of System Interrupts to the Apic Local Unit Eisa and IRQ13 MultiProcessor Specification Bios Post Initialization System Bios Programming Guidelines Controlling the Application Processors Programming the Apic for Virtual Wire Mode System Bios Programming Guidelines Example A-1. Programming Local Apic for Virtual Wire Mode NMI Constructing the MP Configuration Table System Bios Programming Guidelines Page Operating System Programming Guidelines Operating System Boot-up Interrupt Mode Initialization and Handling Operating System Booting and Self-configuration Operating System Programming Guidelines Application Processor Startup Using Init IPI AP Shutdown Handling Using Startup IPI Handling TLB Invalidation Other IPI ApplicationsSpurious Apic Interrupts Handling Cache Flush Supporting Unequal Processors Page System Compliance Checklist Page Variable Interrupt Routing Interrupt Routing with Multiple APICs Fixed Interrupt Routing INTD# Bus Entries in Systems with More Than One PCI BusI/O Interrupt Assignment Entries for PCI Devices Multiple I/O Apic Multiple PCI Bus SystemsPage Errata 126 System Address Space Entry System Address Space Mapping Entries Address Base 14. System Address Space Mapping Entry FieldsEntry Length Address Type Space records must also be provided Bus Hierarchy Descriptor Entry Parent BUS BUS Informationsd Glossary Glossary-2 Order Number