Default Configurations
| BSP |
| AP |
| |
| PENTIIUM (735\90, 815\100) |
| PENTIUM (735\90, 815\100) | ||
| CPU1 |
| CPU2 | ||
APICEN | LOCAL | APICEN | LOCAL | ||
| APIC |
| APIC | ||
REG. |
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| |
MARK |
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| |
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| INTR/LINT0 |
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| |
NMI |
| NMI/LINT1 |
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| |
INIT |
| INIT |
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| |
SMI# |
| SMI# |
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| |
| ICC BUS |
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| |
IRQ1 |
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| 0 |
| |
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| 1 |
| |
A |
| 3 | 2 |
| |
| 3 |
| |||
| 4 |
| |||
8254 TIMER |
| 4 |
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| 5 |
| |||
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| 5 |
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| 6 |
| ||
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| 6 | I/O | ||
|
| 7 | |||
IRQ8# | INT8 | 7 | |||
| APIC | ||||
|
| 9 | 8 | ||
|
| 9 |
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| 10 |
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| 10 |
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| 11 |
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| 11 |
| ||
IRQ13 |
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| 13 | 12 |
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| 13 |
| ||
B |
| 14 |
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| 14 |
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| 15 |
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| 15 |
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EISA DMA CHAINING |
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FROM BSP |
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FERR# | FERR |
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| 0 |
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IGNNE# |
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SAMPLING |
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| 1 |
| ||
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| 3 |
| 2 | MASTER INTR |
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| 3 | ||
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| 4 |
| 4 | 8259A PIC |
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| 5 |
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| 5 |
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| 6 |
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ABFULL | ABFULL |
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| 6 |
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| 7 |
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| 7 |
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(PS/2 MOUSE) | SAMPLING |
| 12 |
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C |
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| 0 |
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EDGE/LEVEL TRIGGER |
| 9 | 1 |
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| |
POLARITY CONTROL |
| 10 | 2 |
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| |
| 11 | SLAVE | ||||
| D |
| 3 | |||
| 12 | |||||
IRQx |
|
| 4 | 8259A PIC | ||
PIRQ |
| 5 |
|
| ||
LITMx | 14 |
| IMCR | |||
| 6 |
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| MAPPING | 15 |
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| 7 |
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| E0 | ||||
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SHADED AREAS:
A,B: MAY NOT BE EXTERNALIZED WITH SOME EISA CHIPSETS
B,C: EISA BUS SPECIFIC
D: PCI BUS SPECIFIC
Figure 5-2. Default Configuration for Integrated APIC
Two local interrupt input pins, LINT0 and LINT1, are shared with the INTR and NMI pins, respectively. The LINT0, LINT1, SMI# and INIT signals are switched by APICEN, and they
Version 1.4 |
