Contents
Figures
Conceptual Overview | ||
Memory Layout Conventions | ||
Multiprocessor System Architecture | ||
APIC Configuration | ||
System Memory Address Map | ||
PIC Mode | ||
Virtual Wire Mode via Local APIC | ||
Virtual Wire Mode via I/O APIC | ||
Symmetric I/O Mode | ||
Multiple I/O APIC Configurations | ||
MP Configuration Data Structures | ||
MP Floating Pointer Structure | ||
MP Configuration Table Header | ||
Processor Entry | ||
Bus Entry | ||
I/O APIC Entry | ||
I/O Interrupt Entry | ||
Local Interrupt Entry | ||
System Address Space Entry | ||
Example System with Multiple Bus Types and Bridge Types | ||
Bus Hierarchy Descriptor Entry | ||
Compatibility Bus Address Space Modifier Entry | ||
Default Configuration for Discrete APIC | ||
Default Configuration for Integrated APIC |
Tables
Document Organization | ||
Memory Cacheability Map | ||
APIC Versions | ||
Processor Entry Fields | ||
Intel486™ and Pentium ® Processor Signatures |
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