Target Audience, Document Organization | Intel MultiProcessor

Introduction

In addition to the hardware requirements, this document also specifies MP features that are visible to the BIOS and operating system. However, it is important to understand that as hardware technology progresses, the functions performed by the BIOS may change in accordance with the hardware technology. ONLY THE INTERFACE TO THE OPERATING SYSTEM LEVEL

IS EXPECTED TO REMAIN CONSTANT.

This specification does not address issues relating to the processor's System Management Mode (SMM).

1.4 Target Audience

This document is intended for the following users:

∙OEMs who will be creating PC/AT-compatible, MP-ready hardware based on this specification.

∙BIOS developers, either those who create general-purpose BIOS products or those who modify these products to suit specific MP hardware.

∙Operating-system developers who will be adapting MP operating systems to run on the class of MP-ready platform specified here.

1.5Organization of This Document

Table 1-1 shows the organization of this document.

Table 1-1. Document Organization

Chapter	Description
2	Overview of the MultiProcessor Specification

3	Specification of the MP hardware

4	Specification of MP configuration information available to OS

5	Specification of default hardware configurations

Appendix A	Guidelines for MP BIOS programming

Appendix B	Guidelines for MP operating system programming

Appendix C	Checklist for hardware compliance to the specification

Appendix D	Clarifications for multiple I/O APIC, multiple PCI bus systems

Glossary	Definitions of specialized terms used in this document

	Version 1.4	1-3

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Intel MultiProcessor manual Target Audience, Organization of This Document, Document Organization, Introduction

Contents

MultiProcessor Specification Copyright 1993-1997. Intel Corporation, All Rights Reserved Revision Revision History Date Revision HistoryPage Table of Contents Default Configurations MP Configuration TableContents Appendix B Operating System Programming Guidelines Appendix a System Bios Programming GuidelinesAppendix E Errata Glossary Tables Figures Examples Page Conceptual Overview Goals MultiProcessor Specification Features of the SpecificationScope Organization of This Document Target AudienceDocument Organization Introduction For More Information Conventions Used in This Document System Overview System Processors Hardware Overview System Overview Advanced Programmable Interrupt Controller 4 I/O Expansion Bus System Memory Operating System Overview Bios OverviewPage System Memory Configuration Hardware Specification System Memory Address Map System Memory Cacheability and Shareability Memory Cacheability Map Hardware Specification Locking External Cache Subsystem Multiprocessor Interrupt Control Posted Memory WriteApic Architecture Apic Versions Interrupt Modes PIC Mode PIC Mode Virtual Wire Mode via Local Apic Virtual Wire Mode Virtual Wire Mode via I/O Apic Symmetric I/O Mode Symmetric I/O Mode Floating Point Exception Interrupt Assignment of System Interrupts to the Apic Local UnitApic Memory Mapping Apic Identification Apic Interval Timers System-wide Reset Reset Support Processor-specific Init System-wide Init System Initial State Support for Fault-resilient Booting MP Configuration Table MultiProcessor Specification MP Floating Pointer Structure MP Configuration TableOffset Length Field Bytesbits in bits Description Offset Length Field Bytesbits Bits Description MP FeatureInformation Byte Information Bytes MP Configuration Table Header MP Configuration Table Header MP Configuration Table Header Fields Base MP Configuration Table EntriesOffset Length Field Bytes Bits Description Processor Entries Base MP Configuration Table Entry TypesLength Entry Description Entry Type Code Bytes Comments Apic Processor Entry Fields Intel486 and Pentium Processor Signatures Feature Flags from Cpuid InstructionFamily Model Stepping a Description Bit Name Description Comments BUS ID Bus EntriesBUS Type String Bus Type String Description Bus Type String Values 4 I/O Interrupt Assignment Entries 3 I/O Apic EntriesApic Entry I/O Apic Entry Fields I/O Interrupt Entry 10. I/O Interrupt Entry Fields 11. Interrupt Type Values Local Interrupt Assignment EntriesInterrupt Type Description Comments Destination Local Apic ID 12. Local Interrupt Entry FieldsDestination Local Apic LINTIN# Extended MP Configuration Table Entries System Address Space Mapping Entries 14. System Address Space Mapping Entry Fields 10. Example System with Multiple Bus Types and Bridge Types Bus Hierarchy Descriptor Entry Compatibility Bus Address Space Modifier Entry 12. Compatibility Bus Address Space Modifier Entry 16. Compatibility Bus Address Space Modifier Entry Fields Default Configurations Default Configurations Discrete Apic ConfigurationsDefault Number Bus Config Code CPUs Type Variant Schematic Default Configurations Default Configuration for Discrete Apic Integrated Apic Configurations Default Configuration for Integrated Apic Config INTINx Comments Default Configuration Interrupt AssignmentsAssignment of I/O Interrupts to the Apic I/O Unit First I/O Assignment of System Interrupts to the Apic Local Unit All Local APICs Config LINTINx CommentsEisa and IRQ13 Level-triggered Interrupt Support MultiProcessor Specification Bios Post Initialization System Bios Programming Guidelines Controlling the Application Processors Programming the Apic for Virtual Wire Mode System Bios Programming Guidelines Example A-1. Programming Local Apic for Virtual Wire Mode NMI Constructing the MP Configuration Table System Bios Programming Guidelines Page Operating System Programming Guidelines Operating System Boot-up Interrupt Mode Initialization and Handling Operating System Booting and Self-configuration Operating System Programming Guidelines Application Processor Startup Using Init IPI AP Shutdown Handling Using Startup IPI Spurious Apic Interrupts Other IPI ApplicationsHandling Cache Flush Handling TLB Invalidation Supporting Unequal Processors Page System Compliance Checklist Page Variable Interrupt Routing Interrupt Routing with Multiple APICs Fixed Interrupt Routing I/O Interrupt Assignment Entries for PCI Devices Bus Entries in Systems with More Than One PCI BusMultiple I/O Apic Multiple PCI Bus Systems INTD#Page Errata 126 System Address Space Entry System Address Space Mapping Entries Entry Length 14. System Address Space Mapping Entry FieldsAddress Type Address Base Space records must also be provided Bus Hierarchy Descriptor Entry Parent BUS BUS Informationsd Glossary Glossary-2 Order Number