Intel MultiProcessor manual 3.6.2Interrupt Modes

MultiProcessor Specification

Table 3-2. APIC Versions

	Local APIC Version
APIC Type	Register (hexadecimal)	Integrated APIC Features
82489DX APIC	0x
Integrated APIC, i.e.,	1x	STARTUP IPI. See Appendix B.4.2 for details.
Pentium processors (735\90,		Programmable interrupt input polarity
815\100)

NOTE:

x is a 4-bit hexadecimal number.

To encourage future extendibility and innovation, the Intel APIC architecture definition is limited to the programming interface of the APIC units. The ICC bus protocol and electrical specifications are considered implementation-specific. That is, while different versions of APIC implementations may execute the same binary software, different versions of APIC components may be implemented with different bus protocols or electrical specifications. Care must be taken when using different versions of the APIC in a system.

The APIC architecture is designed to be scaleable. The 82489DX APIC has an 8-bit ID register that can address from one to 255 APIC devices. Furthermore, the Logical Destination register for the 82489DX APIC supports 32 bits, which can address up to 32 devices. For small system implementations, the APIC ID register can be reduced to the least significant 4 bits and the Logical Destination register can be reduced to the most significant 8 bits.

To ensure software compatibility with all versions of APIC implementations, software developers must follow the following programming guidelines:

1.Assign an 8-bit APIC ID starting from zero.

2.Assign logical destinations starting from the most significant byte of the 32-bit register.

3.Program the APIC spurious vector to hexadecimal “ xF,” where x is a 4-bit hexadecimal number.

The following features are only available in the integrated APIC:

1.The I/O APIC interrupt input signal polarity can be programmable.

2.A new interprocessor interrupt, STARTUP IPI is defined.

In general, the operating system must use the STARTUP IPI to wake up application processors in systems with integrated APICs, but must use INIT IPI in systems with the 82489DX APIC. Refer to Appendix B, Section B.4, for application processor startup.

3.6.2Interrupt Modes

The MP specification defines three different interrupt modes as follows:

1.PIC Mode— effectively bypasses all APIC components and forces the system to operate in single-processor mode.

2.Virtual Wire Mode—uses an APIC as a virtual wire, but otherwise operates the same as PIC Mode.

3.Symmetric I/O Mode—enables the system to operate with more than one processor.

3-6 Version 1.4