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Intel MultiProcessor manual 3.6.2.3Symmetric I/O Mode, 5.Symmetric I/O Mode

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3.6.2.3Symmetric I/O Mode

Hardware Specification

3.6.2.3Symmetric I/O Mode

Some MP operating systems operate in Symmetric I/O Mode. This mode requires at least one I/O APIC to operate. In this mode, I/O interrupts are generated by the I/O APIC. All 8259 interrupt lines are either masked or work together with the I/O APIC in a mixed mode. See Figure 3-5 for an overview of Symmetric I/O Mode.

BSP		AP1		AP2
CPU 1		CPU 2		CPU 3

	NMI	INTR		NMI INTR		NMI	INTR
		LOCAL		LOCAL			LOCAL
REG.		APIC		APIC			APIC
REG.		1		2				3
MARK	LINTIN0		LINTIN1	LINTIN0	LINTIN1	LINTIN0		LINTIN1
	LINTIN0		LINTIN1	LINTIN0	LINTIN1	LINTIN0		LINTIN1
LINTIN1
LINTIN0
RESET
ICC BUS
NMI
				8259A-	INTR
				EQUIVALENT
				PICS
INTERRUPT INPUTS								I/O
INTERRUPT INPUTS							APIC
							APIC

SHADED AREAS INDICATE UNUSED CIRCUITS. DOTTED LINE SHOWS INTERRUPT PATH.

Figure 3-5. Symmetric I/O Mode

The APIC I/O unit has general-purpose interrupt inputs that can be individually programmed to different operating modes. The I/O APIC interrupt line assignments are system implementation specific. Refer to Chapter 4 for custom implementations and to Chapter 5 for default configurations.

The hardware must support a mode of operation in which the system can switch easily to Symmetric I/O mode from PIC or Virtual Wire mode. When the operating system is ready to switch to MP operation, it writes a 01H to the IMCR register, if that register is implemented, and enables I/O APIC Redirection Table entries. The hardware must not require any other action on the part of software to make the transition to Symmetric I/O mode.

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Intel MultiProcessor manual 3.6.2.3Symmetric I/O Mode, 5.Symmetric I/O Mode

Contents

Version MultiProcessor SpecificationIntel Corporation Literature Center P.O. Box Date Revision HistoryRevision Revision HistoryPage Chapter 2 System Overview Table of ContentsChapter 3 Hardware Specification Chapter 1 IntroductionChapter 5 Default Configurations Chapter 4 MP Configuration TableAppendix C System Compliance Checklist Appendix A System BIOS Programming GuidelinesAppendix E Errata Glossary Tables FiguresExamples Page 1.1 Goals 1 Introduction1.3Scope 1.2 Features of the Specification1.5Organization of This Document 1.4 Target AudienceIS EXPECTED TO REMAIN CONSTANT 1.7 For More Information 1.6 Conventions Used in This DocumentIN THE RESERVED FIELDS Version 2 System Overview2.1.1System Processors 2.1 Hardware Overview2.1.2Advanced Programmable Interrupt Controller Figure 2-2.APIC Configuration2.1.4I/O Expansion Bus 2.1.3System Memory2.3 Operating System Overview 2.2 BIOS OverviewPage 3.1 System Memory Configuration 3 Hardware SpecificationFigure 3-1.System Memory Address Map 3.2 System Memory Cacheability and ShareabilityShared by All Hardware SpecificationTable 3-1.Memory Cacheability Map Addresses3.4Locking 3.3 External Cache Subsystem3.6 Multiprocessor Interrupt Control 3.5 Posted Memory Write3.6.1APIC Architecture 3.6.2Interrupt Modes Version 3.6.2.1PIC ModeFigure 3-2.PIC Mode Figure 3-3.Virtual Wire Mode via Local APIC 3.6.2.2Virtual Wire Mode3-10 Figure 3-4.Virtual Wire Mode via I/O APICFigure 3-5.Symmetric I/O Mode 3.6.2.3Symmetric I/O Mode3.6.5APIC Memory Mapping 3.6.4Floating Point Exception Interrupt3.6.8Multiple I/O APIC Configurations 3.6.7APIC Interval Timers3.6.6APIC Identification 3.7.1System-wideRESET 3.7 RESET Support3-15 3.7.2System-wideINIT3.7.3Processor-specificINIT Version3.8 System Initial State 3.9 Support for Fault-resilientBootingFigure 4-1.MP Configuration Data Structures 4 MP Configuration TableThe following two data structures are used Figure 4-2.MP Floating Pointer Structure 4.1MP Floating Pointer StructureTable 4-1.MP Floating Pointer Structure Fields Field MultiProcessor SpecificationOffset LengthFigure 4-3.MP Configuration Table Header 4.2MP Configuration Table Header1CH 10H ENTRY TYPE 4.3BaseMP Configuration Table Entries4.3.1Processor Entries Table 4-3. BaseMP Configuration TableEntry TypesFigure 4-4.Processor Entry Table 4-4.Processor Entry Fields Model Table 4-6.Feature Flags from CPUID InstructionMP Configuration Table FamilyFigure 4-5.Bus Entry Table 4-7.Bus Entry Fields 4.3.2 Bus EntriesDescription MP Configuration TableTable 4-8.Bus Type String Values Bus Type StringTable 4-9.I/O APIC Entry Fields 4.3.3 I/O APIC Entries4.3.4 I/O Interrupt Assignment Entries I/O APIC EntryVersion Figure 4-7.I/O Interrupt Entry4-13 Table 4-10.I/O Interrupt Entry Fields Table 4-11.Interrupt Type Values 4.3.5Local Interrupt Assignment EntriesFigure 4-8.Local Interrupt Entry Length MultiProcessor SpecificationTable 4-12.Local Interrupt Entry Fields Offset in4.4Extended MP Configuration Table Entries Figure 4-9.System Address Space Entry 4.4.1System Address Space Mapping EntriesField MP Configuration TableOffset LengthSince all device settings must fall within supported System Address Space mapping for a given bus in order to be usable by the operating system, buses that do not support dynamically configurable devices i.e., ISA, EISA should support all possible addresses to that bus Figure 4-11.Bus Hierarchy Descriptor Entry 4.4.2Bus Hierarchy Descriptor EntryField Table 4-15Bus Hierarchy Descriptor Entry FieldsOffset LengthADDRESS MOD Version4-23 PREDEFINED RANGE LISTTable 4-17.Predefined Range Lists 5 Default Configurations Table 5-1.Default Configurations 5.1 Discrete APIC ConfigurationsMARK Default ConfigurationsVersion SHADED AREAS5.2 Integrated APIC Configurations MARK VersionSHADED AREAS B,C EISA BUS SPECIFIC D PCI BUS SPECIFICMultiProcessor Specification 5.3.2Level-triggeredInterrupt Support 5.3.1EISA and IRQ13The 8259A INTR output signal is connected to the LINTIN0 of all local APICs, which makes INTR dynamically routable via software. NMI is connected to the LINTIN1 of all local APICs, which makes NMI dynamically routable via software A.1 BIOS Post Initialization A System BIOS Programming GuidelinesA.2 Controlling the Application Processors A.3 Programming the APIC for Virtual Wire ModeVersion System BIOS Programming GuidelinesA.4 Constructing the MP Configuration Table Version Page B.1 Operating System Boot-up B Operating System Programming GuidelinesB.3 Interrupt Mode Initialization and Handling Example B-1.Universal Start-upAlgorithm B.4 Application Processor StartupB.4.1 USINGINIT IPI B.5 APShutdown Handling B.4.2 USINGSTARTUP IPIB.6.2 Handling TLB Invalidation B.6 Other IPI ApplicationsB.7 Spurious APIC Interrupts B.6.1 Handling Cache FlushVersion B.8 Supporting Unequal ProcessorsPage Any NO answer indicates non-compliance C System Compliance ChecklistCondition Page D.1 Interrupt Routing with Multiple APICs D Multiple I/O APIC Multiple PCI Bus SystemsD.1.1 Variable Interrupt Routing D.1.2 Fixed Interrupt Routing Field Multiple I/O APIC Multiple PCI Bus SystemsOffset LengthPage Version E ErrataSIGNATURE Figure 4-9.System Address Space Entry 4.4.1 System Address Space Mapping EntriesENTRY TYPE space records must also be provided 4.4.2 Bus Hierarchy Descriptor EntryTable 4-15Bus Hierarchy Descriptor Entry Fields Figure 4-11.Bus Hierarchy Descriptor EntryGlossary Glossary-2 Order Number