Motorola MVME2300 Series manual Raven Registers, MPC Registers

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Raven PCI Bridge ASIC

When the FLBRD bit is set, Raven will handle read transactions originating from the MPC bus in the following manner:

❏Write-posted transactions originating from the processor bus are flushed by the nature of the FIFO architecture. The Raven will hold the processor with wait states until the PCI-bound FIFO is empty.

❏Write-posted transactions originating from the PCI bus are flushed whenever the PCI slave has accepted a write-posted transaction and the transaction has not completed on the MPC bus.

Raven Registers

This section provides a detailed description of all registers in the Raven ASIC. The registers are organized in two groups: MPC registers and PCI Configuration registers. The MPC registers are accessible only from the MPC bus, but accept any valid transfer size. The PCI Configuration registers reside in PCI configuration space. They are accessible from the MPC bus through the Raven ASIC.

The MPC registers are described first; the PCI Configuration registers are described next. A complete discussion of the RavenMPIC registers can be found later in this chapter.

The following conventions are used in the Raven register charts:

❏ R Read Only field.

❏ R/W Read/Write field.

❏ S Writing a ONE to this field sets this field.

❏ C Writing a ONE to this field clears this field.

MPC Registers

The Raven MPC register map is shown in Table 2-7.

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