Motorola MVME2300 Series manual MPC Error Enable Register, Matom

Raven Registers

MPC Error Enable Register

Address														$FEFF0020
Bit											1	1	1	1	1	1	1	1	1	1	2	2	2	2	2	2	2	2	2	2	3	3
	0	1	2	3	4	5	6	7	8	9	0	1	2	3	4	5	6	7	8	9	0	1	2	3	4	5	6	7	8	9	0	1
Name																							MEREN
																		DFLT	MATOM		PERRM	SERRM	SMAM	RTAM			MATOII		PERRI	SERRI	SMAI	RTAI
Operation				R								R					R	R/W	R/W	R	R/W	R/W	R/W	R/W	R	R	R/W	R	R/W	R/W	R/W	R/W
Reset				$00								$00					0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
				DFLT					Default MPC Master ID. This bit determines which
									MCHK∗ pin will be asserted for error conditions in which
									the MPC master ID cannot be determined or the Raven
									was the MPC master. For example, in event of a PCI
									parity error for a transaction in which the Raven’s PCI
									master was not involved, the MPC master ID cannot be
									determined. When DFLT is set, MCHK1∗ is used. When
									DFLT is clear, MCHK0∗ is used.
				MATOM					MPC Address Bus Time-out Machine Check Enable.
									When this bit is set, the MATO bit in the MERST register
									is used to assert the MCHK output to the current address
									bus master. When this bit is clear, MCHK is not asserted.
				PERRM					PCI Parity Error Machine Check Enable. When this
									bit is set, the PERR bit in the MERST register is used to
									assert the MCHK output to bus master 0. When this bit is
									clear, MCHK is not asserted.
				SERRM					PCI System Error Machine Check Enable. When this
									bit is set, the SERR bit in the MERST register is used to
									assert the MCHK output to bus master 0. When this bit is
									clear, MCHK is not asserted.

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