3

Falcon ECC Memory Controller Chip Set

Data Paths

Because of the Falcon “pair” architecture, data paths can be confusing. Figure 3-10attempts to show the placement of data that is written by a PowerPC master to DRAM. Table 3-22shows the same information in tabular format.

 

 

 

 

 

 

 

 

 

ra12=0

ra12=1

 

 

 

 

 

 

 

 

rd63

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

a[27:28]=0

a[27:28]=1

a[27:28]=2

a[27:28]=3

rd31

 

 

 

DRAM

 

 

 

 

 

 

 

 

rd32

 

 

 

Lower Falcon’s

dl31

 

 

 

 

 

 

 

rd0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PowerPC dl0

Data dh31

ra12=0

ra12=1

dh0

rd63

 

rd32

 

Upper Falcon’s

rd31

 

 

 

DRAM

rd0

1909 9609

Figure 3-10. PowerPC Data to DRAM Data Correspondence

3-60

Computer Group Literature Center Web Site

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Image 222
Motorola MVME2300 Series manual Data Paths, PowerPC Data to Dram Data Correspondence