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Motorola MVME2300 Series manual Parity, Cache Support, PCI Write Posting, PCI Master

Models: MVME2300 Series

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Functional Description

Parity

The PCI slave supports address parity error detection, data parity generation and data parity error detection.

Cache Support

The PCI slave does not participate in the PCI caching protocol.

PCI Write Posting

If write-posting is enabled, the Raven stores the target address, attributes, and up to 128 bytes of data from one PCI write transaction and immediately acknowledges the transaction on the PCI bus. This allows the slower PCI to continue to transfer data at its maximum bandwidth, and the faster MPC bus to accept data in high-performance cache-line burst transfers.

Only one PCI transaction may be write-posted at any given time. If the Raven is busy processing a previous write-posted transaction when a new PCI transaction begins, the next PCI transaction is delayed (TRDY∗ is not asserted) until the previous transaction has completed. If during a transaction the write-post buffer is filled, subsequent PCI data transfers are delayed (TRDY∗ is not asserted) until the Raven has removed some data from the FIFO. Under normal conditions, the Raven should be able to empty the FIFO faster than the PCI bus can fill it.

PCI Configuration cycles intended for internal Raven registers are also delayed if the Raven is busy, so that control bits which may affect write- posting do not change until all write-posted transactions have completed.

PCI Master

The PCI master, in conjunction with the capabilities of the MPC slave, will attempt to move data in either single-beat or four-beat (burst) transactions. All single-beat transactions will be subdivided into one or two 32-bit transfers, depending on the alignment and size of the transaction. The PCI master will attempt to transfer all four-beat transactions in 64-bit mode if the PCI bus has 64-bit mode enabled. If at any time during the transaction the PCI target indicates that it cannot support 64-bit mode, the PCI master will continue to transfer the remaining data in 32-bit mode.

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Motorola MVME2300 Series manual Parity, Cache Support, PCI Write Posting, PCI Master

Contents

MVME2300 Series VME Processor Module Programmer’s Reference GuidePage Safety Summary Instructions FlammabilityCE Notice European Community Limited and Restricted Rights Legend Contents Raven PCI Bridge Asic Page Page Falcon ECC Memory Controller Chip Set Universe VMEbus to PCI Chip Chapter Page List of Figures Page List of Tables Xviii 64MB ECC Dram Model Memory Processor16MB ECC Dram 32MB ECC DramDate Description of Change Summary of ChangesComments and Suggestions Overview of ContentsCtrl Conventions Used in This ManualBold Enter, Return or CRXxiii Xxiv Overview IntroductionECC Dram Summary of FeaturesFeatures MVME2300 Series Feature MVME2300Scsa I/O System Block DiagramBoard Description and Memory Maps MVME2300 Series System Block Diagram Functional Description VMEbus InterfaceFront Panel P2 I/O Programming ModelPCI interface Processor Memory MapsProcessor Address Size Definition Start End Default Processor Memory MapChrp Memory Map Example Processor Chrp Memory MapAddress Register Name Register Value Raven MPC Register Values for Chrp Memory MapProcessor Prep Memory Map Prep Memory Map ExampleBfff Ffff Raven MPC Register Values for Prep Memory Map PCI Configuration AccessPCI Address Size Definition Start End Default PCI Memory MapPCI Memory Maps PCI Chrp Memory MapFC03 Ffff Configuration Register Value Address Offset Register Name Raven PCI Register Values for Chrp Memory MapUniverse PCI Register Values for Chrp Memory Map 10. PCI Prep Memory Map PCI Prep Memory Map3AFE Ffff 38FF Ffff39FE Ffff 39FF Ffff11. Raven PCI Register Values for Prep Memory Map 12. Universe PCI Register Values for Prep Memory Map VMEbus Master Map VMEbus MappingVMEbus Slave Map VMEbus Slave Mapping VSI0TO VSI0CTLVSI0BS VSI0BD15. System Register Summary VMEbus Address Size Chrp Map Prep Map Range ModeFalcon-Controlled System Registers 14. VMEbus Slave Map ExampleSysclk Value System Clock Speed PCI Clock Speed System Configuration Register SyscrSystem Configuration Register $FEF80400 $FDP0/1STAT Value Processor 0/1 Present External In-line Cache MSIZE01 Total Memory On Board Memory Configuration Register MemcrMemory Configuration Register $FEF80404 MSIZE01MSPD01 RA/BTYP02L2TYPE03 PLL Value Size L2PLL03FLSHP02 System External Cache Control Register SxccrCPU Control Register $FEF88300 Processor 0 External Cache Control Register P0XCCRProcessor 1 External Cache Control Register P1XCCR CPU Control RegisterUart Access RegistersISA Local Resource Bus W83C553 PIB RegistersGeneral-Purpose Readable Jumpers NVRAM/RTC and Watchdog Timer RegistersPCI I/O Address Function Module Configuration and Status Registers17. M48T59/559 Access Registers 18. Module Configuration and Status RegistersSD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 CPU Configuration RegisterOld CPU Configuration Register $FE000800 CputypeBase Module Feature Register Base Module Feature Register Offset $0802Pcixp PMC2P PMC1P Vmep Lanp Basetype Base Module Status Register BmsrBasetype Base Module Status Register Offset $0803SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 VME RegistersSeven-Segment Display Register Segment Display Register Offset $08C0SETSIG0 19. VME RegistersLM/SIG Control Register SETSIG1LM/SIG Status Register Board Description and Memory Maps Location Monitor Lower Base Address Register Offset $1003 Location Monitor Upper Base Address RegisterLocation Monitor Lower Base Address Register Location Monitor Upper Base Address Register Offset $1002Semaphore Register 2 Offset $1005 Semaphore RegisterSemaphore Register 1 Offset $1004 SEM1Emulated Z8536 Registers Emulated Z8536 CIO Registers and Port Pins20. Emulated Z8536 Access Registers VME Geographical Address Register VgarZ8536 CIO Port Pins Port Signal Direction Descriptions Pin Name21. Z8536 CIO Port Pin Assignments ISA DMA Channels PC2 BASETYP0PC3 BASETYP1 Page Features Features of the Raven AsicFunction Features Block Diagram Raven Block Diagram MPC Address Mapping MPC Bus InterfaceMPC-to-PCI Address Decoding MPC Slave MPC to PCI Address TranslationMPC Transfer Type Transaction Encoding Command Types MPC Slave ResponseMPC Master MPC Write PostingPCI Command Code MPC Transfer TypesMPC Transfer Type MPC Transfer Size TT0-TT4 MPC Arbiter MPC Bus TimerPCI Address Mapping Configuration RegistersPCI to MPC Address Decoding MPC Bus Address SpaceDecoder Priority RavenMPIC Control RegistersPCI Slave Addressing Command TypesCommand Types PCI Slave Response Command Type Slave Response?Fast Back-to-Back Transactions Exclusive AccessDevice Selection Target-Initiated TerminationPCI Master ParityCache Support PCI Write PostingTransfer Type PCI Master Command CodesPCI Command Entity AddressedMaster Initiated Termination Combining, Merging, and CollapsingArbitration Arbitration LatencyAddress/Data Stepping Generating PCI Cycles Generating PCI Memory and I/O CyclesPCI Cycle Type PCI Spread I/O Address Translation Generating PCI Configuration CyclesFunctional Description Device Number Address Bit Generating PCI Special CyclesWhen MPC Devices are Big-Endian Endian ConversionGenerating PCI Interrupt Acknowledge Cycles Big- to Little-Endian Data Swap Data Address Length Bytes Modification When MPC Devices are Little-EndianRaven Registers and Endian Mode Address Modification for Little-Endian TransfersError Handling Perr Error Status Error Address AttributesTransaction Ordering SMAMPC Registers Raven RegistersRaven MPC Register Map Vendor ID/Device ID Registers VenidDevid Revision ID. Identifies the Raven revision level. This General Control-Status/Feature RegistersRevision ID Register RevidMpic FlbrdBhog MarbMIDx FeatCurrent MPC Data Bus Master MPC Arbiter Control Register Prescaler Adjust RegisterOperation Reset $00 Operation Reset $00 $B4Matom MPC Error Enable RegisterPerri SmamRtam MatoiMPC Error Status Register OVFMato RTA Writing it to a 0 has no effect. When the Smam bitSMA PCI transaction. The bit may be cleared by writing it to aTTx MPC Error Attribute Register MeratWhich originated the transfer in which the error occurred RegisterDesignates a selected byte Address $FEFF0030 Bit Name Operation Reset $0000PCI Interrupt Acknowledge Register PiackMPC Slave Address 3 Register Operation Reset $8000 $8080Start ENDWEN MPC Slave Offset/Attribute 0,1 and 2 RegistersMSOFFx RENWpen IOMMSOFF3 PCI Registers Cycles. When clear, the corresponding MPC slave will$8C Raven PCI Configuration Register Map$0C $18 $7FOffset $00 Bit Name Operation Reset $4801 $1057Raven PCI I/O Register Map $CF8PCI Command/ Status Registers Rcvta DparSeltim SigtaSpace Revision ID/ Class Code RegistersClass Base RegisterPRE RESIoba IO/MEMTo access MPC bus resources. The value of this field will PCI Slave Address 0,1,2 and 3 RegistersBe compared with the upper 16 bits of the incoming PCI GBL PCI Slave Attribute/ Offset 0,1,2 and 3 RegistersINV Transfer type code which specifies the current transactionConfigaddress Register Perspective from the MPC bus in Big-Endian modeConceptual perspective from the PCI bus DEV Perspective from the MPC bus in Little-Endian modeREG FUNEN Enable Configdata RegisterBUS Data ‘B’ Data ‘C’ Data ‘D’ Operation Reset Data ‘D’ Data ‘C’ Data ‘B’ Data ‘A’ Operation ResetFeatures Raven Interrupt ControllerArchitecture Readability of CSR Interrupt Source PriorityProcessor’s Current Task Priority Compatibility Nesting of Interrupt EventsSpurious Vector Generation Interprocessor Interrupts IPITimers Raven-Detected ErrorsInterrupt Delivery Modes Raven Interrupt Controller Block Diagram DescriptionProgram-Visible Registers Interrupt Pending Register IPRInterrupt Selector is In-Service Register ISR Interrupt Request Register IRRInterrupt Router Raven PCI Bridge Asic Off Mpic RegistersRavenMPIC Registers 10. RavenMPIC Register Map$010E0 $010F0$011E0 $100F0 $100E0$101F0 $101E0Feature Reporting Register NcpuVID Offset $01020 Bit Name Global Configuration RegisterProcessor Init Register Processor 1. Writing a 1 to P1 will assert the Soft ResetVendor Identification Register STPPrior IPI Vector/Priority RegistersMask ACTOffset $010E0 Bit Name Spurious Vector RegisterInterrupt Acknowledge register is read during a spurious Vector fetchTimer Base Count Registers Timer Current Count RegistersBit transitions from a 1 to a 0, the value is copied into Count Inhibit. Setting this bit to 1 inhibits counting forThis timer. Setting the bit to 0 allows counting to proceed Base Count. This field contains the 31-bit count for thisTimer Destination Registers Sense Setting this bit to a 0 enables active low or negative edgeExternal Source Vector/Priority Registers POLExternal Source Destination Registers Offset $10200 Bit Name Raven-Detected Errors Vector/Priority RegisterOffset $10210 Bit Name Raven-Detected Errors Destination RegisterOffset Processor $20080 $21080 Bit Name End Of Interrupt. There is one EOI register per Zero is assumed. Writing to this register signals the endInterrupt Acknowledge Registers End-of-Interrupt RegistersProgramming Notes External Interrupt ServiceReset State Interprocessor Interrupts Dynamically Changing I/O Interrupt ConfigurationCurrent Task Priority Level EOI RegisterInterrupt Acknowledge Register ModeArchitectural Notes Page Dram Features of the Falcon Chip SetFalcon Pair Used with Dram in a System Block DiagramsFalcon Internal Data Paths Simplified Overall Dram Connections Bit Ordering Convention PerformanceFour-beat Reads/Writes Dram Speeds Single-beat Reads/WritesBeat PowerPC 60x Bus to Dram Access Timing 70ns Page DevicesClock Periods Required For Total Access Type 2nd 3rd 4th2nd 3rd 4th Clocks Beat PowerPC 60x Bus to Dram Access Timing 60ns Page DevicesPowerPC Bus to Dram Access Timing 50ns Hyper Devices ROM/Flash Speeds Cache Coherency PowerPC 60x Bus InterfaceResponding to Address Transfers Completing Data TransfersCache Coherency Restrictions L2 Cache SupportCycle Types Single-Bit Error ReportingError Logging Dram TesterROM/Flash Interface Functional Description $XXFFFFFB $7FFFFF $XXFFFFF8 $7FFFFC$XXFFFFF9 $7FFFFD $XXFFFFFA $7FFFFE$X3FFFFF3 $7FFFFE $X3FFFFF0 $7FFFFE$X3FFFFF1 $7FFFFE $X3FFFFF2 $7FFFFEBlocks a and/or B Present, Blocks C and D Not Present Refresh/ScrubBlocks a and/or B Present, Blocks C and/or D Present Dram Arbitration Chip DefaultsCSR Accesses External Register SetCSR Architecture Data Path for Reads from the Falcon Internal CSRs Data Path for Writes to the Falcon Internal CSRs Memory Map for Byte Reads to CSR 1906 Memory Map for 4-Byte Reads to CSR Detailed Register Bit Descriptions Register Summary10. Register Summary Test D3 Lower 32 Bits Programming ModelAddress $FEF80000 Bit Name Vendor/Device RegisterRead Zero Read only Revision ID/ General Control RegisterRam spd0,ram spd1 11. ram spd1,ram spd0 and Dram TypeRam spd0, ram spd1 Dram Speed Dram Type Dram Attributes Register Ram a/b/c/d enRam a/b/c/d siz0-2 SIMM/DIMM BlockA/B/C/D ConfigurationsRam a/b/c/d Block Size Devices Used Technology Comments 0MBCLK Frequency Dram Base RegisterRAM A/B/C/D Base CLK Frequency RegisterRead Zero ECC Control RegisterRefdis Rwcb11707.00 Falcon ECC Memory Controller Chip Set Mcken TienSien MienElog Embt EsenAddress $FEF80038 Bit Name Error Address Register13. rtest Encodings Rtest0,rtest1,rtest2 Test Mode selectedAddress $FEF80048 Bit Name Refresh/Scrub Address Register1Mbyte of Block a also appears at $FFF00000 ROM a Base1MB 14. ROM Block a Size Encoding15. romarv and rombrv Encoding Rom a siz Block SizeCycle Transfer Alignment Romx64 Romxwe Falcon Response 16. Read/Write to ROM/FlashROM B Base/Size Register ROM B Base1Mbyte of Block B also appears at $FFF00000 Rom b siz Block Size 17. ROM Block B Size EncodingHas been programmed properly. Notice that CTR32 is Dram Tester Control RegistersBit Counter CTR32 is a 32-bit, free-running counter that incrementsPower-Up Reset Status Register Address $FEF80400 Bit NameAddress $FEF80500 Bit Name Address $FEF88000 $FEF8FFF8 Bit Name External Register SetWriting to the Control Registers Parity Checking on the PowerPC BusSoftware Considerations Programming ROM/Flash DevicesSizing Dram Software Considerations ROW 19. PowerPC 60x Address to Dram Address Mappings18. Sizing Addresses 1024MB 256MB 128MB 64MB 32MB 16MB20. Syndrome Codes Ordered by Bit in Error ECC CodesBit Syndrome 20. Syndrome Codes Ordered by Bit in Error $AF $CF $EF 21. Single-Bit Errors Ordered by Syndrome CodeData Paths 10. PowerPC Data to Dram Data Correspondence22. PowerPC Data to Dram Data Mapping Page Universe VMEbus to PCI Chip − BLT, ADOH, RMW, Lock Features of the Universe AsicBlock Diagram Universe as VMEbus Slave Architectural Diagram for the UniverseUniverse as VMEbus Master PCI Bus InterfaceUniverse as PCI Slave Universe as PCI Master InterrupterVMEbus Interrupt Handling DMA ControllerUniverse Control and Status Registers Ucsr Ucsr Access Mechanisms Universe Register Map Offset Register Name LSI3BS LSI2BSLSI2BD LSI2TOLinten DcppDgcs DllueVSI2BS VSI0BD F0CVSI1BS F1C VSI2CTL F2CDescription Universe Chip Problems after PCI ResetMethod WorkaroundsExamples Example 1 MVME2600 Series Board Exhibits PCI Reset ProblemExample 2 MVME3600 Series Board Acts Differently Run the init code and the LSI0 registers become Example 3 Universe Chip is Checked at Tundra Universe VMEbus to PCI Chip PIB PCI ArbitrationPCI Arbitration Assignments Pci Bus Request PCI MastersMVME2300 Series Interrupt Architecture Interrupt HandlingLevel RavenMPICRavenMPIC Interrupt Assignments Edge Polarity Interrupt SourceInterrupts IRQ14IRQ15 PIB Interrupt Handler Block Diagram Edge PIB PCI/ISA Interrupt AssignmentsISA DMA Channels Sources of Reset Reset switchExceptions Devices Affected Soft ResetReset Sources and Devices Affected Sources of ResetError Notification and Handling Error Notification and HandlingCause Action Big-Endian Mode Endian IssuesLittle-Endian Mode PCI/Ethernet Processor/Memory DomainRole of the Raven Asic PCI DomainRole of the Universe Asic VMEbus DomainPCI-Graphics ROM/Flash Bank Default Default Mapping for FFF00000-FFFFFFFFROM/Flash Initialization Page Document Title Publication Number Motorola Computer Group DocumentsDocument Title and Source Publication Number Manufacturers’ DocumentsEK-DE500-OM MPCFPE/ADRelated Specifications ANSI/IEEEIEC 821 BUS MPR-PPC-RPU-02 IsbnTIA/EIA-232 Page Glossary O S S a R Y Enhanced Integrated Drive Electronics. An improved version PCI. Used in the reference platform specification. IBM IBM Computers developed by the IBM Corporation. PowerPC isSignal Computing System Architecture. a hardware model for See 10base-2 Page Index PCI 1-13 processor IN-3 PCI MPCIN-5 Configaddress 2-56CONFIGDATA IN-7 IN-8